﻿<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
<EDKSYSTEM EDWVERSION="1.2" TIMESTAMP="Sun Apr 12 14:18:14 2026" VIVADOVERSION="2021.2">

  <SYSTEMINFO ARCH="zynq" DEVICE="7z020" NAME="system" PACKAGE="clg400" SPEEDGRADE="-1"/>

  <EXTERNALPORTS>
    <PORT DIR="I" LEFT="15" NAME="adc_dat_a_i" RIGHT="0" SIGIS="undef" SIGNAME="External_Ports_adc_dat_a_i">
      <CONNECTIONS>
        <CONNECTION INSTANCE="adc_0" PORT="adc_dat_a"/>
      </CONNECTIONS>
    </PORT>
    <PORT DIR="I" LEFT="15" NAME="adc_dat_b_i" RIGHT="0" SIGIS="undef" SIGNAME="External_Ports_adc_dat_b_i">
      <CONNECTIONS>
        <CONNECTION INSTANCE="adc_0" PORT="adc_dat_b"/>
      </CONNECTIONS>
    </PORT>
    <PORT DIR="I" NAME="adc_clk_p_i" SIGIS="undef" SIGNAME="External_Ports_adc_clk_p_i">
      <CONNECTIONS>
        <CONNECTION INSTANCE="pll_0" PORT="clk_in1_p"/>
      </CONNECTIONS>
    </PORT>
    <PORT DIR="I" NAME="adc_clk_n_i" SIGIS="undef" SIGNAME="External_Ports_adc_clk_n_i">
      <CONNECTIONS>
        <CONNECTION INSTANCE="pll_0" PORT="clk_in1_n"/>
      </CONNECTIONS>
    </PORT>
    <PORT DIR="O" NAME="adc_enc_p_o" SIGIS="undef"/>
    <PORT DIR="O" NAME="adc_enc_n_o" SIGIS="undef"/>
    <PORT DIR="O" NAME="adc_csn_o" SIGIS="undef" SIGNAME="adc_0_adc_csn">
      <CONNECTIONS>
        <CONNECTION INSTANCE="adc_0" PORT="adc_csn"/>
      </CONNECTIONS>
    </PORT>
    <PORT DIR="O" LEFT="13" NAME="dac_dat_o" RIGHT="0" SIGIS="undef" SIGNAME="dac_0_dac_dat">
      <CONNECTIONS>
        <CONNECTION INSTANCE="dac_0" PORT="dac_dat"/>
      </CONNECTIONS>
    </PORT>
    <PORT DIR="O" NAME="dac_clk_o" SIGIS="undef" SIGNAME="dac_0_dac_clk">
      <CONNECTIONS>
        <CONNECTION INSTANCE="dac_0" PORT="dac_clk"/>
      </CONNECTIONS>
    </PORT>
    <PORT DIR="O" NAME="dac_rst_o" POLARITY="ACTIVE_LOW" SIGIS="undef" SIGNAME="dac_0_dac_rst">
      <CONNECTIONS>
        <CONNECTION INSTANCE="dac_0" PORT="dac_rst"/>
      </CONNECTIONS>
    </PORT>
    <PORT DIR="O" NAME="dac_sel_o" SIGIS="undef" SIGNAME="dac_0_dac_sel">
      <CONNECTIONS>
        <CONNECTION INSTANCE="dac_0" PORT="dac_sel"/>
      </CONNECTIONS>
    </PORT>
    <PORT DIR="O" NAME="dac_wrt_o" SIGIS="undef" SIGNAME="dac_0_dac_wrt">
      <CONNECTIONS>
        <CONNECTION INSTANCE="dac_0" PORT="dac_wrt"/>
      </CONNECTIONS>
    </PORT>
    <PORT DIR="O" LEFT="3" NAME="dac_pwm_o" RIGHT="0" SIGIS="undef"/>
    <PORT DIR="IO" LEFT="7" NAME="exp_p_tri_io" RIGHT="0" SIGIS="undef"/>
    <PORT DIR="IO" LEFT="7" NAME="exp_n_tri_io" RIGHT="0" SIGIS="undef" SIGNAME="External_Ports_exp_n_tri_io">
      <CONNECTIONS>
        <CONNECTION INSTANCE="io_bridge_out" PORT="io"/>
      </CONNECTIONS>
    </PORT>
    <PORT DIR="O" LEFT="7" NAME="led_o" RIGHT="0" SIGIS="undef"/>
    <PORT DIR="IO" NAME="DDR_cas_n" SIGIS="undef" SIGNAME="ps_0_DDR_CAS_n">
      <CONNECTIONS>
        <CONNECTION INSTANCE="ps_0" PORT="DDR_CAS_n"/>
      </CONNECTIONS>
    </PORT>
    <PORT DIR="IO" NAME="DDR_cke" SIGIS="undef" SIGNAME="ps_0_DDR_CKE">
      <CONNECTIONS>
        <CONNECTION INSTANCE="ps_0" PORT="DDR_CKE"/>
      </CONNECTIONS>
    </PORT>
    <PORT CLKFREQUENCY="100000000" DIR="IO" NAME="DDR_ck_n" SIGIS="clk" SIGNAME="ps_0_DDR_Clk_n">
      <CONNECTIONS>
        <CONNECTION INSTANCE="ps_0" PORT="DDR_Clk_n"/>
      </CONNECTIONS>
    </PORT>
    <PORT CLKFREQUENCY="100000000" DIR="IO" NAME="DDR_ck_p" SIGIS="clk" SIGNAME="ps_0_DDR_Clk">
      <CONNECTIONS>
        <CONNECTION INSTANCE="ps_0" PORT="DDR_Clk"/>
      </CONNECTIONS>
    </PORT>
    <PORT DIR="IO" NAME="DDR_cs_n" SIGIS="undef" SIGNAME="ps_0_DDR_CS_n">
      <CONNECTIONS>
        <CONNECTION INSTANCE="ps_0" PORT="DDR_CS_n"/>
      </CONNECTIONS>
    </PORT>
    <PORT DIR="IO" NAME="DDR_reset_n" POLARITY="ACTIVE_LOW" SIGIS="rst" SIGNAME="ps_0_DDR_DRSTB">
      <CONNECTIONS>
        <CONNECTION INSTANCE="ps_0" PORT="DDR_DRSTB"/>
      </CONNECTIONS>
    </PORT>
    <PORT DIR="IO" NAME="DDR_odt" SIGIS="undef" SIGNAME="ps_0_DDR_ODT">
      <CONNECTIONS>
        <CONNECTION INSTANCE="ps_0" PORT="DDR_ODT"/>
      </CONNECTIONS>
    </PORT>
    <PORT DIR="IO" NAME="DDR_ras_n" SIGIS="undef" SIGNAME="ps_0_DDR_RAS_n">
      <CONNECTIONS>
        <CONNECTION INSTANCE="ps_0" PORT="DDR_RAS_n"/>
      </CONNECTIONS>
    </PORT>
    <PORT DIR="IO" NAME="DDR_we_n" SIGIS="undef" SIGNAME="ps_0_DDR_WEB">
      <CONNECTIONS>
        <CONNECTION INSTANCE="ps_0" PORT="DDR_WEB"/>
      </CONNECTIONS>
    </PORT>
    <PORT DIR="IO" LEFT="2" NAME="DDR_ba" RIGHT="0" SIGIS="undef" SIGNAME="ps_0_DDR_BankAddr">
      <CONNECTIONS>
        <CONNECTION INSTANCE="ps_0" PORT="DDR_BankAddr"/>
      </CONNECTIONS>
    </PORT>
    <PORT DIR="IO" LEFT="14" NAME="DDR_addr" RIGHT="0" SIGIS="undef" SIGNAME="ps_0_DDR_Addr">
      <CONNECTIONS>
        <CONNECTION INSTANCE="ps_0" PORT="DDR_Addr"/>
      </CONNECTIONS>
    </PORT>
    <PORT DIR="IO" LEFT="3" NAME="DDR_dm" RIGHT="0" SIGIS="undef" SIGNAME="ps_0_DDR_DM">
      <CONNECTIONS>
        <CONNECTION INSTANCE="ps_0" PORT="DDR_DM"/>
      </CONNECTIONS>
    </PORT>
    <PORT DIR="IO" LEFT="31" NAME="DDR_dq" RIGHT="0" SIGIS="undef" SIGNAME="ps_0_DDR_DQ">
      <CONNECTIONS>
        <CONNECTION INSTANCE="ps_0" PORT="DDR_DQ"/>
      </CONNECTIONS>
    </PORT>
    <PORT DIR="IO" LEFT="3" NAME="DDR_dqs_n" RIGHT="0" SIGIS="undef" SIGNAME="ps_0_DDR_DQS_n">
      <CONNECTIONS>
        <CONNECTION INSTANCE="ps_0" PORT="DDR_DQS_n"/>
      </CONNECTIONS>
    </PORT>
    <PORT DIR="IO" LEFT="3" NAME="DDR_dqs_p" RIGHT="0" SIGIS="undef" SIGNAME="ps_0_DDR_DQS">
      <CONNECTIONS>
        <CONNECTION INSTANCE="ps_0" PORT="DDR_DQS"/>
      </CONNECTIONS>
    </PORT>
    <PORT DIR="IO" LEFT="53" NAME="FIXED_IO_mio" RIGHT="0" SIGIS="undef" SIGNAME="ps_0_MIO">
      <CONNECTIONS>
        <CONNECTION INSTANCE="ps_0" PORT="MIO"/>
      </CONNECTIONS>
    </PORT>
    <PORT DIR="IO" NAME="FIXED_IO_ddr_vrn" SIGIS="undef" SIGNAME="ps_0_DDR_VRN">
      <CONNECTIONS>
        <CONNECTION INSTANCE="ps_0" PORT="DDR_VRN"/>
      </CONNECTIONS>
    </PORT>
    <PORT DIR="IO" NAME="FIXED_IO_ddr_vrp" SIGIS="undef" SIGNAME="ps_0_DDR_VRP">
      <CONNECTIONS>
        <CONNECTION INSTANCE="ps_0" PORT="DDR_VRP"/>
      </CONNECTIONS>
    </PORT>
    <PORT DIR="IO" NAME="FIXED_IO_ps_srstb" SIGIS="undef" SIGNAME="ps_0_PS_SRSTB">
      <CONNECTIONS>
        <CONNECTION INSTANCE="ps_0" PORT="PS_SRSTB"/>
      </CONNECTIONS>
    </PORT>
    <PORT DIR="IO" NAME="FIXED_IO_ps_clk" SIGIS="undef" SIGNAME="ps_0_PS_CLK">
      <CONNECTIONS>
        <CONNECTION INSTANCE="ps_0" PORT="PS_CLK"/>
      </CONNECTIONS>
    </PORT>
    <PORT DIR="IO" NAME="FIXED_IO_ps_porb" SIGIS="undef" SIGNAME="ps_0_PS_PORB">
      <CONNECTIONS>
        <CONNECTION INSTANCE="ps_0" PORT="PS_PORB"/>
      </CONNECTIONS>
    </PORT>
  </EXTERNALPORTS>

  <EXTERNALINTERFACES>
    <BUSINTERFACE BUSNAME="__NOC__" NAME="Vp_Vn" TYPE="TARGET">
      <PORTMAPS/>
    </BUSINTERFACE>
    <BUSINTERFACE BUSNAME="__NOC__" NAME="Vaux0" TYPE="TARGET">
      <PORTMAPS/>
    </BUSINTERFACE>
    <BUSINTERFACE BUSNAME="__NOC__" NAME="Vaux1" TYPE="TARGET">
      <PORTMAPS/>
    </BUSINTERFACE>
    <BUSINTERFACE BUSNAME="__NOC__" NAME="Vaux9" TYPE="TARGET">
      <PORTMAPS/>
    </BUSINTERFACE>
    <BUSINTERFACE BUSNAME="__NOC__" NAME="Vaux8" TYPE="TARGET">
      <PORTMAPS/>
    </BUSINTERFACE>
    <BUSINTERFACE BUSNAME="ps_0_DDR" DATAWIDTH="8" NAME="DDR" TYPE="INITIATOR">
      <PARAMETER NAME="CAN_DEBUG" VALUE="false"/>
      <PARAMETER NAME="TIMEPERIOD_PS" VALUE="1250"/>
      <PARAMETER NAME="MEMORY_TYPE" VALUE="COMPONENTS"/>
      <PARAMETER NAME="MEMORY_PART"/>
      <PARAMETER NAME="DATA_WIDTH" VALUE="8"/>
      <PARAMETER NAME="CS_ENABLED" VALUE="true"/>
      <PARAMETER NAME="DATA_MASK_ENABLED" VALUE="true"/>
      <PARAMETER NAME="SLOT" VALUE="Single"/>
      <PARAMETER NAME="CUSTOM_PARTS"/>
      <PARAMETER NAME="MEM_ADDR_MAP" VALUE="ROW_COLUMN_BANK"/>
      <PARAMETER NAME="BURST_LENGTH" VALUE="8"/>
      <PARAMETER NAME="AXI_ARBITRATION_SCHEME" VALUE="TDM"/>
      <PARAMETER NAME="CAS_LATENCY" VALUE="11"/>
      <PARAMETER NAME="CAS_WRITE_LATENCY" VALUE="11"/>
      <PORTMAPS>
        <PORTMAP LOGICAL="CAS_N" PHYSICAL="DDR_cas_n"/>
        <PORTMAP LOGICAL="CKE" PHYSICAL="DDR_cke"/>
        <PORTMAP LOGICAL="CK_N" PHYSICAL="DDR_ck_n"/>
        <PORTMAP LOGICAL="CK_P" PHYSICAL="DDR_ck_p"/>
        <PORTMAP LOGICAL="CS_N" PHYSICAL="DDR_cs_n"/>
        <PORTMAP LOGICAL="RESET_N" PHYSICAL="DDR_reset_n"/>
        <PORTMAP LOGICAL="ODT" PHYSICAL="DDR_odt"/>
        <PORTMAP LOGICAL="RAS_N" PHYSICAL="DDR_ras_n"/>
        <PORTMAP LOGICAL="WE_N" PHYSICAL="DDR_we_n"/>
        <PORTMAP LOGICAL="BA" PHYSICAL="DDR_ba"/>
        <PORTMAP LOGICAL="ADDR" PHYSICAL="DDR_addr"/>
        <PORTMAP LOGICAL="DM" PHYSICAL="DDR_dm"/>
        <PORTMAP LOGICAL="DQ" PHYSICAL="DDR_dq"/>
        <PORTMAP LOGICAL="DQS_N" PHYSICAL="DDR_dqs_n"/>
        <PORTMAP LOGICAL="DQS_P" PHYSICAL="DDR_dqs_p"/>
      </PORTMAPS>
    </BUSINTERFACE>
    <BUSINTERFACE BUSNAME="ps_0_FIXED_IO" NAME="FIXED_IO" TYPE="INITIATOR">
      <PARAMETER NAME="CAN_DEBUG" VALUE="false"/>
      <PORTMAPS>
        <PORTMAP LOGICAL="MIO" PHYSICAL="FIXED_IO_mio"/>
        <PORTMAP LOGICAL="DDR_VRN" PHYSICAL="FIXED_IO_ddr_vrn"/>
        <PORTMAP LOGICAL="DDR_VRP" PHYSICAL="FIXED_IO_ddr_vrp"/>
        <PORTMAP LOGICAL="PS_SRSTB" PHYSICAL="FIXED_IO_ps_srstb"/>
        <PORTMAP LOGICAL="PS_CLK" PHYSICAL="FIXED_IO_ps_clk"/>
        <PORTMAP LOGICAL="PS_PORB" PHYSICAL="FIXED_IO_ps_porb"/>
      </PORTMAPS>
    </BUSINTERFACE>
  </EXTERNALINTERFACES>

  <MODULES>
    <MODULE COREREVISION="1" FULLNAME="/adc_0" HWVERSION="1.0" INSTANCE="adc_0" IPTYPE="PERIPHERAL" IS_ENABLE="1" MODCLASS="PERIPHERAL" MODTYPE="axis_red_pitaya_adc" VLNV="pavel-demin:user:axis_red_pitaya_adc:1.0">
      <DOCUMENTS/>
      <PARAMETERS>
        <PARAMETER NAME="ADC_DATA_WIDTH" VALUE="16"/>
        <PARAMETER NAME="Component_Name" VALUE="system_adc_0_0"/>
        <PARAMETER NAME="EDK_IPTYPE" VALUE="PERIPHERAL"/>
      </PARAMETERS>
      <PORTS>
        <PORT CLKFREQUENCY="122880000" DIR="I" NAME="aclk" SIGIS="clk" SIGNAME="pll_0_clk_out1">
          <CONNECTIONS>
            <CONNECTION INSTANCE="pll_0" PORT="clk_out1"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" NAME="adc_csn" SIGIS="undef" SIGNAME="adc_0_adc_csn">
          <CONNECTIONS>
            <CONNECTION INSTANCE="External_Ports" PORT="adc_csn_o"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" LEFT="15" NAME="adc_dat_a" RIGHT="0" SIGIS="undef" SIGNAME="External_Ports_adc_dat_a_i">
          <CONNECTIONS>
            <CONNECTION INSTANCE="External_Ports" PORT="adc_dat_a_i"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" LEFT="15" NAME="adc_dat_b" RIGHT="0" SIGIS="undef" SIGNAME="External_Ports_adc_dat_b_i">
          <CONNECTIONS>
            <CONNECTION INSTANCE="External_Ports" PORT="adc_dat_b_i"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" NAME="m_axis_tvalid" SIGIS="undef"/>
        <PORT DIR="O" LEFT="31" NAME="m_axis_tdata" RIGHT="0" SIGIS="undef" SIGNAME="adc_0_m_axis_tdata">
          <CONNECTIONS>
            <CONNECTION INSTANCE="adc_slice_0" PORT="din"/>
            <CONNECTION INSTANCE="adc_slice_1" PORT="din"/>
            <CONNECTION INSTANCE="adc_slice_2" PORT="din"/>
            <CONNECTION INSTANCE="adc_slice_3" PORT="din"/>
          </CONNECTIONS>
        </PORT>
      </PORTS>
      <BUSINTERFACES>
        <BUSINTERFACE BUSNAME="__NOC__" NAME="m_axis" TYPE="INITIATOR" VLNV="xilinx.com:interface:axis:1.0">
          <PARAMETER NAME="TDATA_NUM_BYTES" VALUE="4"/>
          <PARAMETER NAME="TDEST_WIDTH" VALUE="0"/>
          <PARAMETER NAME="TID_WIDTH" VALUE="0"/>
          <PARAMETER NAME="TUSER_WIDTH" VALUE="0"/>
          <PARAMETER NAME="HAS_TREADY" VALUE="0"/>
          <PARAMETER NAME="HAS_TSTRB" VALUE="0"/>
          <PARAMETER NAME="HAS_TKEEP" VALUE="0"/>
          <PARAMETER NAME="HAS_TLAST" VALUE="0"/>
          <PARAMETER NAME="FREQ_HZ" VALUE="122880000"/>
          <PARAMETER NAME="PHASE" VALUE="0.0"/>
          <PARAMETER NAME="CLK_DOMAIN" VALUE="system_pll_0_0_clk_out1"/>
          <PARAMETER NAME="LAYERED_METADATA" VALUE="undef"/>
          <PARAMETER NAME="INSERT_VIP" VALUE="0"/>
          <PORTMAPS>
            <PORTMAP LOGICAL="TDATA" PHYSICAL="m_axis_tdata"/>
            <PORTMAP LOGICAL="TVALID" PHYSICAL="m_axis_tvalid"/>
          </PORTMAPS>
        </BUSINTERFACE>
      </BUSINTERFACES>
    </MODULE>
    <MODULE COREREVISION="1" FULLNAME="/adc_slice_0" HWVERSION="1.0" INSTANCE="adc_slice_0" IPTYPE="PERIPHERAL" IS_ENABLE="1" MODCLASS="PERIPHERAL" MODTYPE="port_slicer" VLNV="pavel-demin:user:port_slicer:1.0">
      <DOCUMENTS/>
      <PARAMETERS>
        <PARAMETER NAME="DIN_WIDTH" VALUE="32"/>
        <PARAMETER NAME="DIN_FROM" VALUE="15"/>
        <PARAMETER NAME="DIN_TO" VALUE="0"/>
        <PARAMETER NAME="Component_Name" VALUE="system_adc_slice_0_0"/>
        <PARAMETER NAME="EDK_IPTYPE" VALUE="PERIPHERAL"/>
      </PARAMETERS>
      <PORTS>
        <PORT DIR="I" LEFT="31" NAME="din" RIGHT="0" SIGIS="undef" SIGNAME="adc_0_m_axis_tdata">
          <CONNECTIONS>
            <CONNECTION INSTANCE="adc_0" PORT="m_axis_tdata"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" LEFT="15" NAME="dout" RIGHT="0" SIGIS="undef" SIGNAME="adc_slice_0_dout">
          <CONNECTIONS>
            <CONNECTION INSTANCE="mult_0" PORT="B"/>
          </CONNECTIONS>
        </PORT>
      </PORTS>
      <BUSINTERFACES/>
    </MODULE>
    <MODULE COREREVISION="1" FULLNAME="/adc_slice_1" HWVERSION="1.0" INSTANCE="adc_slice_1" IPTYPE="PERIPHERAL" IS_ENABLE="1" MODCLASS="PERIPHERAL" MODTYPE="port_slicer" VLNV="pavel-demin:user:port_slicer:1.0">
      <DOCUMENTS/>
      <PARAMETERS>
        <PARAMETER NAME="DIN_WIDTH" VALUE="32"/>
        <PARAMETER NAME="DIN_FROM" VALUE="15"/>
        <PARAMETER NAME="DIN_TO" VALUE="0"/>
        <PARAMETER NAME="Component_Name" VALUE="system_adc_slice_1_0"/>
        <PARAMETER NAME="EDK_IPTYPE" VALUE="PERIPHERAL"/>
      </PARAMETERS>
      <PORTS>
        <PORT DIR="I" LEFT="31" NAME="din" RIGHT="0" SIGIS="undef" SIGNAME="adc_0_m_axis_tdata">
          <CONNECTIONS>
            <CONNECTION INSTANCE="adc_0" PORT="m_axis_tdata"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" LEFT="15" NAME="dout" RIGHT="0" SIGIS="undef" SIGNAME="adc_slice_1_dout">
          <CONNECTIONS>
            <CONNECTION INSTANCE="mult_1" PORT="B"/>
          </CONNECTIONS>
        </PORT>
      </PORTS>
      <BUSINTERFACES/>
    </MODULE>
    <MODULE COREREVISION="1" FULLNAME="/adc_slice_2" HWVERSION="1.0" INSTANCE="adc_slice_2" IPTYPE="PERIPHERAL" IS_ENABLE="1" MODCLASS="PERIPHERAL" MODTYPE="port_slicer" VLNV="pavel-demin:user:port_slicer:1.0">
      <DOCUMENTS/>
      <PARAMETERS>
        <PARAMETER NAME="DIN_WIDTH" VALUE="32"/>
        <PARAMETER NAME="DIN_FROM" VALUE="31"/>
        <PARAMETER NAME="DIN_TO" VALUE="16"/>
        <PARAMETER NAME="Component_Name" VALUE="system_adc_slice_2_0"/>
        <PARAMETER NAME="EDK_IPTYPE" VALUE="PERIPHERAL"/>
      </PARAMETERS>
      <PORTS>
        <PORT DIR="I" LEFT="31" NAME="din" RIGHT="0" SIGIS="undef" SIGNAME="adc_0_m_axis_tdata">
          <CONNECTIONS>
            <CONNECTION INSTANCE="adc_0" PORT="m_axis_tdata"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" LEFT="15" NAME="dout" RIGHT="0" SIGIS="undef" SIGNAME="adc_slice_2_dout">
          <CONNECTIONS>
            <CONNECTION INSTANCE="mult_2" PORT="B"/>
          </CONNECTIONS>
        </PORT>
      </PORTS>
      <BUSINTERFACES/>
    </MODULE>
    <MODULE COREREVISION="1" FULLNAME="/adc_slice_3" HWVERSION="1.0" INSTANCE="adc_slice_3" IPTYPE="PERIPHERAL" IS_ENABLE="1" MODCLASS="PERIPHERAL" MODTYPE="port_slicer" VLNV="pavel-demin:user:port_slicer:1.0">
      <DOCUMENTS/>
      <PARAMETERS>
        <PARAMETER NAME="DIN_WIDTH" VALUE="32"/>
        <PARAMETER NAME="DIN_FROM" VALUE="31"/>
        <PARAMETER NAME="DIN_TO" VALUE="16"/>
        <PARAMETER NAME="Component_Name" VALUE="system_adc_slice_3_0"/>
        <PARAMETER NAME="EDK_IPTYPE" VALUE="PERIPHERAL"/>
      </PARAMETERS>
      <PORTS>
        <PORT DIR="I" LEFT="31" NAME="din" RIGHT="0" SIGIS="undef" SIGNAME="adc_0_m_axis_tdata">
          <CONNECTIONS>
            <CONNECTION INSTANCE="adc_0" PORT="m_axis_tdata"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" LEFT="15" NAME="dout" RIGHT="0" SIGIS="undef" SIGNAME="adc_slice_3_dout">
          <CONNECTIONS>
            <CONNECTION INSTANCE="mult_3" PORT="B"/>
          </CONNECTIONS>
        </PORT>
      </PORTS>
      <BUSINTERFACES/>
    </MODULE>
    <MODULE COREREVISION="15" FULLNAME="/cic_0" HWVERSION="4.0" INSTANCE="cic_0" IPTYPE="PERIPHERAL" IS_ENABLE="1" MODCLASS="PERIPHERAL" MODTYPE="cic_compiler" VLNV="xilinx.com:ip:cic_compiler:4.0">
      <DOCUMENTS>
        <DOCUMENT SOURCE="http://www.xilinx.com/cgi-bin/docs/ipdoc?c=cic_compiler;v=v4_0;d=pg140-cic-compiler.pdf"/>
      </DOCUMENTS>
      <PARAMETERS>
        <PARAMETER NAME="C_COMPONENT_NAME" VALUE="system_cic_0_0"/>
        <PARAMETER NAME="C_FILTER_TYPE" VALUE="1"/>
        <PARAMETER NAME="C_NUM_STAGES" VALUE="6"/>
        <PARAMETER NAME="C_DIFF_DELAY" VALUE="1"/>
        <PARAMETER NAME="C_RATE" VALUE="4"/>
        <PARAMETER NAME="C_INPUT_WIDTH" VALUE="24"/>
        <PARAMETER NAME="C_OUTPUT_WIDTH" VALUE="32"/>
        <PARAMETER NAME="C_USE_DSP" VALUE="0"/>
        <PARAMETER NAME="C_HAS_ROUNDING" VALUE="0"/>
        <PARAMETER NAME="C_NUM_CHANNELS" VALUE="1"/>
        <PARAMETER NAME="C_RATE_TYPE" VALUE="1"/>
        <PARAMETER NAME="C_MIN_RATE" VALUE="4"/>
        <PARAMETER NAME="C_MAX_RATE" VALUE="64"/>
        <PARAMETER NAME="C_SAMPLE_FREQ" VALUE="1"/>
        <PARAMETER NAME="C_CLK_FREQ" VALUE="1"/>
        <PARAMETER NAME="C_USE_STREAMING_INTERFACE" VALUE="1"/>
        <PARAMETER NAME="C_FAMILY" VALUE="zynq"/>
        <PARAMETER NAME="C_XDEVICEFAMILY" VALUE="zynq"/>
        <PARAMETER NAME="C_C1" VALUE="39"/>
        <PARAMETER NAME="C_C2" VALUE="38"/>
        <PARAMETER NAME="C_C3" VALUE="37"/>
        <PARAMETER NAME="C_C4" VALUE="36"/>
        <PARAMETER NAME="C_C5" VALUE="36"/>
        <PARAMETER NAME="C_C6" VALUE="35"/>
        <PARAMETER NAME="C_I1" VALUE="60"/>
        <PARAMETER NAME="C_I2" VALUE="60"/>
        <PARAMETER NAME="C_I3" VALUE="55"/>
        <PARAMETER NAME="C_I4" VALUE="50"/>
        <PARAMETER NAME="C_I5" VALUE="46"/>
        <PARAMETER NAME="C_I6" VALUE="41"/>
        <PARAMETER NAME="C_S_AXIS_CONFIG_TDATA_WIDTH" VALUE="8"/>
        <PARAMETER NAME="C_S_AXIS_DATA_TDATA_WIDTH" VALUE="24"/>
        <PARAMETER NAME="C_M_AXIS_DATA_TDATA_WIDTH" VALUE="32"/>
        <PARAMETER NAME="C_M_AXIS_DATA_TUSER_WIDTH" VALUE="1"/>
        <PARAMETER NAME="C_HAS_DOUT_TREADY" VALUE="0"/>
        <PARAMETER NAME="C_HAS_ACLKEN" VALUE="0"/>
        <PARAMETER NAME="C_HAS_ARESETN" VALUE="1"/>
        <PARAMETER NAME="Component_Name" VALUE="system_cic_0_0"/>
        <PARAMETER NAME="GUI_Behaviour" VALUE="Coregen"/>
        <PARAMETER NAME="Filter_Type" VALUE="Decimation"/>
        <PARAMETER NAME="Number_Of_Stages" VALUE="6"/>
        <PARAMETER NAME="Differential_Delay" VALUE="1"/>
        <PARAMETER NAME="Number_Of_Channels" VALUE="1"/>
        <PARAMETER NAME="Sample_Rate_Changes" VALUE="Programmable"/>
        <PARAMETER NAME="Fixed_Or_Initial_Rate" VALUE="4"/>
        <PARAMETER NAME="Minimum_Rate" VALUE="4"/>
        <PARAMETER NAME="Maximum_Rate" VALUE="64"/>
        <PARAMETER NAME="RateSpecification" VALUE="Frequency_Specification"/>
        <PARAMETER NAME="Input_Sample_Frequency" VALUE="122.88"/>
        <PARAMETER NAME="Clock_Frequency" VALUE="122.88"/>
        <PARAMETER NAME="HardwareOversamplingRate" VALUE="1"/>
        <PARAMETER NAME="SamplePeriod" VALUE="1"/>
        <PARAMETER NAME="Response_Magnitude" VALUE="Normalized"/>
        <PARAMETER NAME="Passband_Min" VALUE="0.0"/>
        <PARAMETER NAME="Stopband_Min" VALUE="0.5"/>
        <PARAMETER NAME="Passband_Max" VALUE="0.5"/>
        <PARAMETER NAME="Stopband_Max" VALUE="1.0"/>
        <PARAMETER NAME="Input_Data_Width" VALUE="24"/>
        <PARAMETER NAME="Quantization" VALUE="Truncation"/>
        <PARAMETER NAME="Output_Data_Width" VALUE="32"/>
        <PARAMETER NAME="Use_Xtreme_DSP_Slice" VALUE="false"/>
        <PARAMETER NAME="Use_Streaming_Interface" VALUE="true"/>
        <PARAMETER NAME="HAS_ACLKEN" VALUE="false"/>
        <PARAMETER NAME="HAS_ARESETN" VALUE="true"/>
        <PARAMETER NAME="HAS_DOUT_TREADY" VALUE="false"/>
        <PARAMETER NAME="EDK_IPTYPE" VALUE="PERIPHERAL"/>
      </PARAMETERS>
      <PORTS>
        <PORT CLKFREQUENCY="122880000" DIR="I" NAME="aclk" SIGIS="clk" SIGNAME="pll_0_clk_out1">
          <CONNECTIONS>
            <CONNECTION INSTANCE="pll_0" PORT="clk_out1"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" NAME="aresetn" POLARITY="ACTIVE_LOW" SIGIS="rst" SIGNAME="slice_0_dout">
          <CONNECTIONS>
            <CONNECTION INSTANCE="slice_0" PORT="dout"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" LEFT="7" NAME="s_axis_config_tdata" RIGHT="0" SIGIS="undef" SIGNAME="cic_0_s_axis_config_tdata">
          <CONNECTIONS>
            <CONNECTION INSTANCE="rate_0" PORT="m_axis_tdata"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" NAME="s_axis_config_tvalid" SIGIS="undef" SIGNAME="cic_0_s_axis_config_tvalid">
          <CONNECTIONS>
            <CONNECTION INSTANCE="rate_0" PORT="m_axis_tvalid"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" NAME="s_axis_config_tready" SIGIS="undef" SIGNAME="cic_0_s_axis_config_tready">
          <CONNECTIONS>
            <CONNECTION INSTANCE="rate_0" PORT="m_axis_tready"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" LEFT="23" NAME="s_axis_data_tdata" RIGHT="0" SIGIS="undef" SIGNAME="mult_0_P">
          <CONNECTIONS>
            <CONNECTION INSTANCE="mult_0" PORT="P"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" NAME="s_axis_data_tvalid" SIGIS="undef" SIGNAME="const_0_dout">
          <CONNECTIONS>
            <CONNECTION INSTANCE="const_0" PORT="dout"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" NAME="s_axis_data_tready" SIGIS="undef"/>
        <PORT DIR="O" LEFT="31" NAME="m_axis_data_tdata" RIGHT="0" SIGIS="undef" SIGNAME="cic_0_m_axis_data_tdata">
          <CONNECTIONS>
            <CONNECTION INSTANCE="comb_0" PORT="s_axis_tdata"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" NAME="m_axis_data_tvalid" SIGIS="undef" SIGNAME="cic_0_m_axis_data_tvalid">
          <CONNECTIONS>
            <CONNECTION INSTANCE="comb_0" PORT="s_axis_tvalid"/>
          </CONNECTIONS>
        </PORT>
      </PORTS>
      <BUSINTERFACES>
        <BUSINTERFACE BUSNAME="__NOC__" NAME="S_AXIS_DATA" TYPE="TARGET" VLNV="xilinx.com:interface:axis:1.0">
          <PARAMETER NAME="TDATA_NUM_BYTES" VALUE="3"/>
          <PARAMETER NAME="TDEST_WIDTH" VALUE="0"/>
          <PARAMETER NAME="TID_WIDTH" VALUE="0"/>
          <PARAMETER NAME="TUSER_WIDTH" VALUE="0"/>
          <PARAMETER NAME="HAS_TREADY" VALUE="1"/>
          <PARAMETER NAME="HAS_TSTRB" VALUE="0"/>
          <PARAMETER NAME="HAS_TKEEP" VALUE="0"/>
          <PARAMETER NAME="HAS_TLAST" VALUE="0"/>
          <PARAMETER NAME="FREQ_HZ" VALUE="122880000"/>
          <PARAMETER NAME="PHASE" VALUE="0.0"/>
          <PARAMETER NAME="CLK_DOMAIN" VALUE="system_pll_0_0_clk_out1"/>
          <PARAMETER NAME="LAYERED_METADATA" VALUE="undef"/>
          <PARAMETER NAME="INSERT_VIP" VALUE="0"/>
          <PORTMAPS>
            <PORTMAP LOGICAL="TDATA" PHYSICAL="s_axis_data_tdata"/>
            <PORTMAP LOGICAL="TREADY" PHYSICAL="s_axis_data_tready"/>
            <PORTMAP LOGICAL="TVALID" PHYSICAL="s_axis_data_tvalid"/>
          </PORTMAPS>
        </BUSINTERFACE>
        <BUSINTERFACE BUSNAME="cic_0_M_AXIS_DATA" NAME="M_AXIS_DATA" TYPE="INITIATOR" VLNV="xilinx.com:interface:axis:1.0">
          <PARAMETER NAME="TDATA_NUM_BYTES" VALUE="4"/>
          <PARAMETER NAME="TDEST_WIDTH" VALUE="0"/>
          <PARAMETER NAME="TID_WIDTH" VALUE="0"/>
          <PARAMETER NAME="TUSER_WIDTH" VALUE="0"/>
          <PARAMETER NAME="HAS_TREADY" VALUE="0"/>
          <PARAMETER NAME="HAS_TSTRB" VALUE="0"/>
          <PARAMETER NAME="HAS_TKEEP" VALUE="0"/>
          <PARAMETER NAME="HAS_TLAST" VALUE="0"/>
          <PARAMETER NAME="FREQ_HZ" VALUE="122880000"/>
          <PARAMETER NAME="PHASE" VALUE="0.0"/>
          <PARAMETER NAME="CLK_DOMAIN" VALUE="system_pll_0_0_clk_out1"/>
          <PARAMETER NAME="LAYERED_METADATA" VALUE="xilinx.com:interface:datatypes:1.0 {TDATA {datatype {name {attribs {resolve_type immediate dependency {} format string minimum {} maximum {}} value {}} bitwidth {attribs {resolve_type automatic dependency {} format long minimum {} maximum {}} value 32} bitoffset {attribs {resolve_type immediate dependency {} format long minimum {} maximum {}} value 0} array_type {name {attribs {resolve_type immediate dependency {} format string minimum {} maximum {}} value chan} size {attribs {resolve_type generated dependency chan_size format long minimum {} maximum {}} value 1} stride {attribs {resolve_type generated dependency chan_stride format long minimum {} maximum {}} value 32} datatype {name {attribs {resolve_type immediate dependency {} format string minimum {} maximum {}} value {}} bitwidth {attribs {resolve_type generated dependency data_width format long minimum {} maximum {}} value 32} bitoffset {attribs {resolve_type immediate dependency {} format long minimum {} maximum {}} value 0} real {fixed {fractwidth {attribs {resolve_type generated dependency data_fractwidth format long minimum {} maximum {}} value 0} signed {attribs {resolve_type immediate dependency {} format bool minimum {} maximum {}} value true}}}}}}} TDATA_WIDTH 32 TUSER {datatype {name {attribs {resolve_type immediate dependency {} format string minimum {} maximum {}} value {}} bitwidth {attribs {resolve_type automatic dependency {} format long minimum {} maximum {}} value 0} bitoffset {attribs {resolve_type immediate dependency {} format long minimum {} maximum {}} value 0} struct {field_chan_out {name {attribs {resolve_type immediate dependency {} format string minimum {} maximum {}} value chan_out} enabled {attribs {resolve_type generated dependency enabled format bool minimum {} maximum {}} value false} datatype {name {attribs {resolve_type immediate dependency {} format string minimum {} maximum {}} value {}} bitwidth {attribs {resolve_type generated dependency chan_out_width format long minimum {} maximum {}} value 0} bitoffset {attribs {resolve_type immediate dependency {} format long minimum {} maximum {}} value 0} integer {signed {attribs {resolve_type immediate dependency {} format bool minimum {} maximum {}} value false}}}} field_chan_sync {name {attribs {resolve_type immediate dependency {} format string minimum {} maximum {}} value chan_sync} enabled {attribs {resolve_type generated dependency enabled format bool minimum {} maximum {}} value false} datatype {name {attribs {resolve_type immediate dependency {} format string minimum {} maximum {}} value {}} bitwidth {attribs {resolve_type generated dependency chan_sync_width format long minimum {} maximum {}} value 0} bitoffset {attribs {resolve_type generated dependency chan_sync_offset format long minimum {} maximum {}} value 0}}}}}} TUSER_WIDTH 0}"/>
          <PARAMETER NAME="INSERT_VIP" VALUE="0"/>
          <PORTMAPS>
            <PORTMAP LOGICAL="TDATA" PHYSICAL="m_axis_data_tdata"/>
            <PORTMAP LOGICAL="TVALID" PHYSICAL="m_axis_data_tvalid"/>
          </PORTMAPS>
        </BUSINTERFACE>
        <BUSINTERFACE BUSNAME="rate_0_m_axis" NAME="S_AXIS_CONFIG" TYPE="TARGET" VLNV="xilinx.com:interface:axis:1.0">
          <PARAMETER NAME="TDATA_NUM_BYTES" VALUE="1"/>
          <PARAMETER NAME="TDEST_WIDTH" VALUE="0"/>
          <PARAMETER NAME="TID_WIDTH" VALUE="0"/>
          <PARAMETER NAME="TUSER_WIDTH" VALUE="0"/>
          <PARAMETER NAME="HAS_TREADY" VALUE="1"/>
          <PARAMETER NAME="HAS_TSTRB" VALUE="0"/>
          <PARAMETER NAME="HAS_TKEEP" VALUE="0"/>
          <PARAMETER NAME="HAS_TLAST" VALUE="0"/>
          <PARAMETER NAME="FREQ_HZ" VALUE="122880000"/>
          <PARAMETER NAME="PHASE" VALUE="0.0"/>
          <PARAMETER NAME="CLK_DOMAIN" VALUE="system_pll_0_0_clk_out1"/>
          <PARAMETER NAME="LAYERED_METADATA" VALUE="undef"/>
          <PARAMETER NAME="INSERT_VIP" VALUE="0"/>
          <PORTMAPS>
            <PORTMAP LOGICAL="TDATA" PHYSICAL="s_axis_config_tdata"/>
            <PORTMAP LOGICAL="TREADY" PHYSICAL="s_axis_config_tready"/>
            <PORTMAP LOGICAL="TVALID" PHYSICAL="s_axis_config_tvalid"/>
          </PORTMAPS>
        </BUSINTERFACE>
      </BUSINTERFACES>
    </MODULE>
    <MODULE COREREVISION="15" FULLNAME="/cic_1" HWVERSION="4.0" INSTANCE="cic_1" IPTYPE="PERIPHERAL" IS_ENABLE="1" MODCLASS="PERIPHERAL" MODTYPE="cic_compiler" VLNV="xilinx.com:ip:cic_compiler:4.0">
      <DOCUMENTS>
        <DOCUMENT SOURCE="http://www.xilinx.com/cgi-bin/docs/ipdoc?c=cic_compiler;v=v4_0;d=pg140-cic-compiler.pdf"/>
      </DOCUMENTS>
      <PARAMETERS>
        <PARAMETER NAME="C_COMPONENT_NAME" VALUE="system_cic_1_0"/>
        <PARAMETER NAME="C_FILTER_TYPE" VALUE="1"/>
        <PARAMETER NAME="C_NUM_STAGES" VALUE="6"/>
        <PARAMETER NAME="C_DIFF_DELAY" VALUE="1"/>
        <PARAMETER NAME="C_RATE" VALUE="4"/>
        <PARAMETER NAME="C_INPUT_WIDTH" VALUE="24"/>
        <PARAMETER NAME="C_OUTPUT_WIDTH" VALUE="32"/>
        <PARAMETER NAME="C_USE_DSP" VALUE="0"/>
        <PARAMETER NAME="C_HAS_ROUNDING" VALUE="0"/>
        <PARAMETER NAME="C_NUM_CHANNELS" VALUE="1"/>
        <PARAMETER NAME="C_RATE_TYPE" VALUE="1"/>
        <PARAMETER NAME="C_MIN_RATE" VALUE="4"/>
        <PARAMETER NAME="C_MAX_RATE" VALUE="64"/>
        <PARAMETER NAME="C_SAMPLE_FREQ" VALUE="1"/>
        <PARAMETER NAME="C_CLK_FREQ" VALUE="1"/>
        <PARAMETER NAME="C_USE_STREAMING_INTERFACE" VALUE="1"/>
        <PARAMETER NAME="C_FAMILY" VALUE="zynq"/>
        <PARAMETER NAME="C_XDEVICEFAMILY" VALUE="zynq"/>
        <PARAMETER NAME="C_C1" VALUE="39"/>
        <PARAMETER NAME="C_C2" VALUE="38"/>
        <PARAMETER NAME="C_C3" VALUE="37"/>
        <PARAMETER NAME="C_C4" VALUE="36"/>
        <PARAMETER NAME="C_C5" VALUE="36"/>
        <PARAMETER NAME="C_C6" VALUE="35"/>
        <PARAMETER NAME="C_I1" VALUE="60"/>
        <PARAMETER NAME="C_I2" VALUE="60"/>
        <PARAMETER NAME="C_I3" VALUE="55"/>
        <PARAMETER NAME="C_I4" VALUE="50"/>
        <PARAMETER NAME="C_I5" VALUE="46"/>
        <PARAMETER NAME="C_I6" VALUE="41"/>
        <PARAMETER NAME="C_S_AXIS_CONFIG_TDATA_WIDTH" VALUE="8"/>
        <PARAMETER NAME="C_S_AXIS_DATA_TDATA_WIDTH" VALUE="24"/>
        <PARAMETER NAME="C_M_AXIS_DATA_TDATA_WIDTH" VALUE="32"/>
        <PARAMETER NAME="C_M_AXIS_DATA_TUSER_WIDTH" VALUE="1"/>
        <PARAMETER NAME="C_HAS_DOUT_TREADY" VALUE="0"/>
        <PARAMETER NAME="C_HAS_ACLKEN" VALUE="0"/>
        <PARAMETER NAME="C_HAS_ARESETN" VALUE="1"/>
        <PARAMETER NAME="Component_Name" VALUE="system_cic_1_0"/>
        <PARAMETER NAME="GUI_Behaviour" VALUE="Coregen"/>
        <PARAMETER NAME="Filter_Type" VALUE="Decimation"/>
        <PARAMETER NAME="Number_Of_Stages" VALUE="6"/>
        <PARAMETER NAME="Differential_Delay" VALUE="1"/>
        <PARAMETER NAME="Number_Of_Channels" VALUE="1"/>
        <PARAMETER NAME="Sample_Rate_Changes" VALUE="Programmable"/>
        <PARAMETER NAME="Fixed_Or_Initial_Rate" VALUE="4"/>
        <PARAMETER NAME="Minimum_Rate" VALUE="4"/>
        <PARAMETER NAME="Maximum_Rate" VALUE="64"/>
        <PARAMETER NAME="RateSpecification" VALUE="Frequency_Specification"/>
        <PARAMETER NAME="Input_Sample_Frequency" VALUE="122.88"/>
        <PARAMETER NAME="Clock_Frequency" VALUE="122.88"/>
        <PARAMETER NAME="HardwareOversamplingRate" VALUE="1"/>
        <PARAMETER NAME="SamplePeriod" VALUE="1"/>
        <PARAMETER NAME="Response_Magnitude" VALUE="Normalized"/>
        <PARAMETER NAME="Passband_Min" VALUE="0.0"/>
        <PARAMETER NAME="Stopband_Min" VALUE="0.5"/>
        <PARAMETER NAME="Passband_Max" VALUE="0.5"/>
        <PARAMETER NAME="Stopband_Max" VALUE="1.0"/>
        <PARAMETER NAME="Input_Data_Width" VALUE="24"/>
        <PARAMETER NAME="Quantization" VALUE="Truncation"/>
        <PARAMETER NAME="Output_Data_Width" VALUE="32"/>
        <PARAMETER NAME="Use_Xtreme_DSP_Slice" VALUE="false"/>
        <PARAMETER NAME="Use_Streaming_Interface" VALUE="true"/>
        <PARAMETER NAME="HAS_ACLKEN" VALUE="false"/>
        <PARAMETER NAME="HAS_ARESETN" VALUE="true"/>
        <PARAMETER NAME="HAS_DOUT_TREADY" VALUE="false"/>
        <PARAMETER NAME="EDK_IPTYPE" VALUE="PERIPHERAL"/>
      </PARAMETERS>
      <PORTS>
        <PORT CLKFREQUENCY="122880000" DIR="I" NAME="aclk" SIGIS="clk" SIGNAME="pll_0_clk_out1">
          <CONNECTIONS>
            <CONNECTION INSTANCE="pll_0" PORT="clk_out1"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" NAME="aresetn" POLARITY="ACTIVE_LOW" SIGIS="rst" SIGNAME="slice_0_dout">
          <CONNECTIONS>
            <CONNECTION INSTANCE="slice_0" PORT="dout"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" LEFT="7" NAME="s_axis_config_tdata" RIGHT="0" SIGIS="undef" SIGNAME="cic_1_s_axis_config_tdata">
          <CONNECTIONS>
            <CONNECTION INSTANCE="rate_1" PORT="m_axis_tdata"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" NAME="s_axis_config_tvalid" SIGIS="undef" SIGNAME="cic_1_s_axis_config_tvalid">
          <CONNECTIONS>
            <CONNECTION INSTANCE="rate_1" PORT="m_axis_tvalid"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" NAME="s_axis_config_tready" SIGIS="undef" SIGNAME="cic_1_s_axis_config_tready">
          <CONNECTIONS>
            <CONNECTION INSTANCE="rate_1" PORT="m_axis_tready"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" LEFT="23" NAME="s_axis_data_tdata" RIGHT="0" SIGIS="undef" SIGNAME="mult_1_P">
          <CONNECTIONS>
            <CONNECTION INSTANCE="mult_1" PORT="P"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" NAME="s_axis_data_tvalid" SIGIS="undef" SIGNAME="const_0_dout">
          <CONNECTIONS>
            <CONNECTION INSTANCE="const_0" PORT="dout"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" NAME="s_axis_data_tready" SIGIS="undef"/>
        <PORT DIR="O" LEFT="31" NAME="m_axis_data_tdata" RIGHT="0" SIGIS="undef" SIGNAME="cic_1_m_axis_data_tdata">
          <CONNECTIONS>
            <CONNECTION INSTANCE="comb_0" PORT="s_axis_tdata"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" NAME="m_axis_data_tvalid" SIGIS="undef" SIGNAME="cic_1_m_axis_data_tvalid">
          <CONNECTIONS>
            <CONNECTION INSTANCE="comb_0" PORT="s_axis_tvalid"/>
          </CONNECTIONS>
        </PORT>
      </PORTS>
      <BUSINTERFACES>
        <BUSINTERFACE BUSNAME="__NOC__" NAME="S_AXIS_DATA" TYPE="TARGET" VLNV="xilinx.com:interface:axis:1.0">
          <PARAMETER NAME="TDATA_NUM_BYTES" VALUE="3"/>
          <PARAMETER NAME="TDEST_WIDTH" VALUE="0"/>
          <PARAMETER NAME="TID_WIDTH" VALUE="0"/>
          <PARAMETER NAME="TUSER_WIDTH" VALUE="0"/>
          <PARAMETER NAME="HAS_TREADY" VALUE="1"/>
          <PARAMETER NAME="HAS_TSTRB" VALUE="0"/>
          <PARAMETER NAME="HAS_TKEEP" VALUE="0"/>
          <PARAMETER NAME="HAS_TLAST" VALUE="0"/>
          <PARAMETER NAME="FREQ_HZ" VALUE="122880000"/>
          <PARAMETER NAME="PHASE" VALUE="0.0"/>
          <PARAMETER NAME="CLK_DOMAIN" VALUE="system_pll_0_0_clk_out1"/>
          <PARAMETER NAME="LAYERED_METADATA" VALUE="undef"/>
          <PARAMETER NAME="INSERT_VIP" VALUE="0"/>
          <PORTMAPS>
            <PORTMAP LOGICAL="TDATA" PHYSICAL="s_axis_data_tdata"/>
            <PORTMAP LOGICAL="TREADY" PHYSICAL="s_axis_data_tready"/>
            <PORTMAP LOGICAL="TVALID" PHYSICAL="s_axis_data_tvalid"/>
          </PORTMAPS>
        </BUSINTERFACE>
        <BUSINTERFACE BUSNAME="cic_1_M_AXIS_DATA" NAME="M_AXIS_DATA" TYPE="INITIATOR" VLNV="xilinx.com:interface:axis:1.0">
          <PARAMETER NAME="TDATA_NUM_BYTES" VALUE="4"/>
          <PARAMETER NAME="TDEST_WIDTH" VALUE="0"/>
          <PARAMETER NAME="TID_WIDTH" VALUE="0"/>
          <PARAMETER NAME="TUSER_WIDTH" VALUE="0"/>
          <PARAMETER NAME="HAS_TREADY" VALUE="0"/>
          <PARAMETER NAME="HAS_TSTRB" VALUE="0"/>
          <PARAMETER NAME="HAS_TKEEP" VALUE="0"/>
          <PARAMETER NAME="HAS_TLAST" VALUE="0"/>
          <PARAMETER NAME="FREQ_HZ" VALUE="122880000"/>
          <PARAMETER NAME="PHASE" VALUE="0.0"/>
          <PARAMETER NAME="CLK_DOMAIN" VALUE="system_pll_0_0_clk_out1"/>
          <PARAMETER NAME="LAYERED_METADATA" VALUE="xilinx.com:interface:datatypes:1.0 {TDATA {datatype {name {attribs {resolve_type immediate dependency {} format string minimum {} maximum {}} value {}} bitwidth {attribs {resolve_type automatic dependency {} format long minimum {} maximum {}} value 32} bitoffset {attribs {resolve_type immediate dependency {} format long minimum {} maximum {}} value 0} array_type {name {attribs {resolve_type immediate dependency {} format string minimum {} maximum {}} value chan} size {attribs {resolve_type generated dependency chan_size format long minimum {} maximum {}} value 1} stride {attribs {resolve_type generated dependency chan_stride format long minimum {} maximum {}} value 32} datatype {name {attribs {resolve_type immediate dependency {} format string minimum {} maximum {}} value {}} bitwidth {attribs {resolve_type generated dependency data_width format long minimum {} maximum {}} value 32} bitoffset {attribs {resolve_type immediate dependency {} format long minimum {} maximum {}} value 0} real {fixed {fractwidth {attribs {resolve_type generated dependency data_fractwidth format long minimum {} maximum {}} value 0} signed {attribs {resolve_type immediate dependency {} format bool minimum {} maximum {}} value true}}}}}}} TDATA_WIDTH 32 TUSER {datatype {name {attribs {resolve_type immediate dependency {} format string minimum {} maximum {}} value {}} bitwidth {attribs {resolve_type automatic dependency {} format long minimum {} maximum {}} value 0} bitoffset {attribs {resolve_type immediate dependency {} format long minimum {} maximum {}} value 0} struct {field_chan_out {name {attribs {resolve_type immediate dependency {} format string minimum {} maximum {}} value chan_out} enabled {attribs {resolve_type generated dependency enabled format bool minimum {} maximum {}} value false} datatype {name {attribs {resolve_type immediate dependency {} format string minimum {} maximum {}} value {}} bitwidth {attribs {resolve_type generated dependency chan_out_width format long minimum {} maximum {}} value 0} bitoffset {attribs {resolve_type immediate dependency {} format long minimum {} maximum {}} value 0} integer {signed {attribs {resolve_type immediate dependency {} format bool minimum {} maximum {}} value false}}}} field_chan_sync {name {attribs {resolve_type immediate dependency {} format string minimum {} maximum {}} value chan_sync} enabled {attribs {resolve_type generated dependency enabled format bool minimum {} maximum {}} value false} datatype {name {attribs {resolve_type immediate dependency {} format string minimum {} maximum {}} value {}} bitwidth {attribs {resolve_type generated dependency chan_sync_width format long minimum {} maximum {}} value 0} bitoffset {attribs {resolve_type generated dependency chan_sync_offset format long minimum {} maximum {}} value 0}}}}}} TUSER_WIDTH 0}"/>
          <PARAMETER NAME="INSERT_VIP" VALUE="0"/>
          <PORTMAPS>
            <PORTMAP LOGICAL="TDATA" PHYSICAL="m_axis_data_tdata"/>
            <PORTMAP LOGICAL="TVALID" PHYSICAL="m_axis_data_tvalid"/>
          </PORTMAPS>
        </BUSINTERFACE>
        <BUSINTERFACE BUSNAME="rate_1_m_axis" NAME="S_AXIS_CONFIG" TYPE="TARGET" VLNV="xilinx.com:interface:axis:1.0">
          <PARAMETER NAME="TDATA_NUM_BYTES" VALUE="1"/>
          <PARAMETER NAME="TDEST_WIDTH" VALUE="0"/>
          <PARAMETER NAME="TID_WIDTH" VALUE="0"/>
          <PARAMETER NAME="TUSER_WIDTH" VALUE="0"/>
          <PARAMETER NAME="HAS_TREADY" VALUE="1"/>
          <PARAMETER NAME="HAS_TSTRB" VALUE="0"/>
          <PARAMETER NAME="HAS_TKEEP" VALUE="0"/>
          <PARAMETER NAME="HAS_TLAST" VALUE="0"/>
          <PARAMETER NAME="FREQ_HZ" VALUE="122880000"/>
          <PARAMETER NAME="PHASE" VALUE="0.0"/>
          <PARAMETER NAME="CLK_DOMAIN" VALUE="system_pll_0_0_clk_out1"/>
          <PARAMETER NAME="LAYERED_METADATA" VALUE="undef"/>
          <PARAMETER NAME="INSERT_VIP" VALUE="0"/>
          <PORTMAPS>
            <PORTMAP LOGICAL="TDATA" PHYSICAL="s_axis_config_tdata"/>
            <PORTMAP LOGICAL="TREADY" PHYSICAL="s_axis_config_tready"/>
            <PORTMAP LOGICAL="TVALID" PHYSICAL="s_axis_config_tvalid"/>
          </PORTMAPS>
        </BUSINTERFACE>
      </BUSINTERFACES>
    </MODULE>
    <MODULE COREREVISION="15" FULLNAME="/cic_2" HWVERSION="4.0" INSTANCE="cic_2" IPTYPE="PERIPHERAL" IS_ENABLE="1" MODCLASS="PERIPHERAL" MODTYPE="cic_compiler" VLNV="xilinx.com:ip:cic_compiler:4.0">
      <DOCUMENTS>
        <DOCUMENT SOURCE="http://www.xilinx.com/cgi-bin/docs/ipdoc?c=cic_compiler;v=v4_0;d=pg140-cic-compiler.pdf"/>
      </DOCUMENTS>
      <PARAMETERS>
        <PARAMETER NAME="C_COMPONENT_NAME" VALUE="system_cic_2_0"/>
        <PARAMETER NAME="C_FILTER_TYPE" VALUE="1"/>
        <PARAMETER NAME="C_NUM_STAGES" VALUE="6"/>
        <PARAMETER NAME="C_DIFF_DELAY" VALUE="1"/>
        <PARAMETER NAME="C_RATE" VALUE="4"/>
        <PARAMETER NAME="C_INPUT_WIDTH" VALUE="24"/>
        <PARAMETER NAME="C_OUTPUT_WIDTH" VALUE="32"/>
        <PARAMETER NAME="C_USE_DSP" VALUE="0"/>
        <PARAMETER NAME="C_HAS_ROUNDING" VALUE="0"/>
        <PARAMETER NAME="C_NUM_CHANNELS" VALUE="1"/>
        <PARAMETER NAME="C_RATE_TYPE" VALUE="1"/>
        <PARAMETER NAME="C_MIN_RATE" VALUE="4"/>
        <PARAMETER NAME="C_MAX_RATE" VALUE="64"/>
        <PARAMETER NAME="C_SAMPLE_FREQ" VALUE="1"/>
        <PARAMETER NAME="C_CLK_FREQ" VALUE="1"/>
        <PARAMETER NAME="C_USE_STREAMING_INTERFACE" VALUE="1"/>
        <PARAMETER NAME="C_FAMILY" VALUE="zynq"/>
        <PARAMETER NAME="C_XDEVICEFAMILY" VALUE="zynq"/>
        <PARAMETER NAME="C_C1" VALUE="39"/>
        <PARAMETER NAME="C_C2" VALUE="38"/>
        <PARAMETER NAME="C_C3" VALUE="37"/>
        <PARAMETER NAME="C_C4" VALUE="36"/>
        <PARAMETER NAME="C_C5" VALUE="36"/>
        <PARAMETER NAME="C_C6" VALUE="35"/>
        <PARAMETER NAME="C_I1" VALUE="60"/>
        <PARAMETER NAME="C_I2" VALUE="60"/>
        <PARAMETER NAME="C_I3" VALUE="55"/>
        <PARAMETER NAME="C_I4" VALUE="50"/>
        <PARAMETER NAME="C_I5" VALUE="46"/>
        <PARAMETER NAME="C_I6" VALUE="41"/>
        <PARAMETER NAME="C_S_AXIS_CONFIG_TDATA_WIDTH" VALUE="8"/>
        <PARAMETER NAME="C_S_AXIS_DATA_TDATA_WIDTH" VALUE="24"/>
        <PARAMETER NAME="C_M_AXIS_DATA_TDATA_WIDTH" VALUE="32"/>
        <PARAMETER NAME="C_M_AXIS_DATA_TUSER_WIDTH" VALUE="1"/>
        <PARAMETER NAME="C_HAS_DOUT_TREADY" VALUE="0"/>
        <PARAMETER NAME="C_HAS_ACLKEN" VALUE="0"/>
        <PARAMETER NAME="C_HAS_ARESETN" VALUE="1"/>
        <PARAMETER NAME="Component_Name" VALUE="system_cic_2_0"/>
        <PARAMETER NAME="GUI_Behaviour" VALUE="Coregen"/>
        <PARAMETER NAME="Filter_Type" VALUE="Decimation"/>
        <PARAMETER NAME="Number_Of_Stages" VALUE="6"/>
        <PARAMETER NAME="Differential_Delay" VALUE="1"/>
        <PARAMETER NAME="Number_Of_Channels" VALUE="1"/>
        <PARAMETER NAME="Sample_Rate_Changes" VALUE="Programmable"/>
        <PARAMETER NAME="Fixed_Or_Initial_Rate" VALUE="4"/>
        <PARAMETER NAME="Minimum_Rate" VALUE="4"/>
        <PARAMETER NAME="Maximum_Rate" VALUE="64"/>
        <PARAMETER NAME="RateSpecification" VALUE="Frequency_Specification"/>
        <PARAMETER NAME="Input_Sample_Frequency" VALUE="122.88"/>
        <PARAMETER NAME="Clock_Frequency" VALUE="122.88"/>
        <PARAMETER NAME="HardwareOversamplingRate" VALUE="1"/>
        <PARAMETER NAME="SamplePeriod" VALUE="1"/>
        <PARAMETER NAME="Response_Magnitude" VALUE="Normalized"/>
        <PARAMETER NAME="Passband_Min" VALUE="0.0"/>
        <PARAMETER NAME="Stopband_Min" VALUE="0.5"/>
        <PARAMETER NAME="Passband_Max" VALUE="0.5"/>
        <PARAMETER NAME="Stopband_Max" VALUE="1.0"/>
        <PARAMETER NAME="Input_Data_Width" VALUE="24"/>
        <PARAMETER NAME="Quantization" VALUE="Truncation"/>
        <PARAMETER NAME="Output_Data_Width" VALUE="32"/>
        <PARAMETER NAME="Use_Xtreme_DSP_Slice" VALUE="false"/>
        <PARAMETER NAME="Use_Streaming_Interface" VALUE="true"/>
        <PARAMETER NAME="HAS_ACLKEN" VALUE="false"/>
        <PARAMETER NAME="HAS_ARESETN" VALUE="true"/>
        <PARAMETER NAME="HAS_DOUT_TREADY" VALUE="false"/>
        <PARAMETER NAME="EDK_IPTYPE" VALUE="PERIPHERAL"/>
      </PARAMETERS>
      <PORTS>
        <PORT CLKFREQUENCY="122880000" DIR="I" NAME="aclk" SIGIS="clk" SIGNAME="pll_0_clk_out1">
          <CONNECTIONS>
            <CONNECTION INSTANCE="pll_0" PORT="clk_out1"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" NAME="aresetn" POLARITY="ACTIVE_LOW" SIGIS="rst" SIGNAME="slice_0_dout">
          <CONNECTIONS>
            <CONNECTION INSTANCE="slice_0" PORT="dout"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" LEFT="7" NAME="s_axis_config_tdata" RIGHT="0" SIGIS="undef" SIGNAME="cic_2_s_axis_config_tdata">
          <CONNECTIONS>
            <CONNECTION INSTANCE="rate_2" PORT="m_axis_tdata"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" NAME="s_axis_config_tvalid" SIGIS="undef" SIGNAME="cic_2_s_axis_config_tvalid">
          <CONNECTIONS>
            <CONNECTION INSTANCE="rate_2" PORT="m_axis_tvalid"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" NAME="s_axis_config_tready" SIGIS="undef" SIGNAME="cic_2_s_axis_config_tready">
          <CONNECTIONS>
            <CONNECTION INSTANCE="rate_2" PORT="m_axis_tready"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" LEFT="23" NAME="s_axis_data_tdata" RIGHT="0" SIGIS="undef" SIGNAME="mult_2_P">
          <CONNECTIONS>
            <CONNECTION INSTANCE="mult_2" PORT="P"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" NAME="s_axis_data_tvalid" SIGIS="undef" SIGNAME="const_0_dout">
          <CONNECTIONS>
            <CONNECTION INSTANCE="const_0" PORT="dout"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" NAME="s_axis_data_tready" SIGIS="undef"/>
        <PORT DIR="O" LEFT="31" NAME="m_axis_data_tdata" RIGHT="0" SIGIS="undef" SIGNAME="cic_2_m_axis_data_tdata">
          <CONNECTIONS>
            <CONNECTION INSTANCE="comb_0" PORT="s_axis_tdata"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" NAME="m_axis_data_tvalid" SIGIS="undef" SIGNAME="cic_2_m_axis_data_tvalid">
          <CONNECTIONS>
            <CONNECTION INSTANCE="comb_0" PORT="s_axis_tvalid"/>
          </CONNECTIONS>
        </PORT>
      </PORTS>
      <BUSINTERFACES>
        <BUSINTERFACE BUSNAME="__NOC__" NAME="S_AXIS_DATA" TYPE="TARGET" VLNV="xilinx.com:interface:axis:1.0">
          <PARAMETER NAME="TDATA_NUM_BYTES" VALUE="3"/>
          <PARAMETER NAME="TDEST_WIDTH" VALUE="0"/>
          <PARAMETER NAME="TID_WIDTH" VALUE="0"/>
          <PARAMETER NAME="TUSER_WIDTH" VALUE="0"/>
          <PARAMETER NAME="HAS_TREADY" VALUE="1"/>
          <PARAMETER NAME="HAS_TSTRB" VALUE="0"/>
          <PARAMETER NAME="HAS_TKEEP" VALUE="0"/>
          <PARAMETER NAME="HAS_TLAST" VALUE="0"/>
          <PARAMETER NAME="FREQ_HZ" VALUE="122880000"/>
          <PARAMETER NAME="PHASE" VALUE="0.0"/>
          <PARAMETER NAME="CLK_DOMAIN" VALUE="system_pll_0_0_clk_out1"/>
          <PARAMETER NAME="LAYERED_METADATA" VALUE="undef"/>
          <PARAMETER NAME="INSERT_VIP" VALUE="0"/>
          <PORTMAPS>
            <PORTMAP LOGICAL="TDATA" PHYSICAL="s_axis_data_tdata"/>
            <PORTMAP LOGICAL="TREADY" PHYSICAL="s_axis_data_tready"/>
            <PORTMAP LOGICAL="TVALID" PHYSICAL="s_axis_data_tvalid"/>
          </PORTMAPS>
        </BUSINTERFACE>
        <BUSINTERFACE BUSNAME="cic_2_M_AXIS_DATA" NAME="M_AXIS_DATA" TYPE="INITIATOR" VLNV="xilinx.com:interface:axis:1.0">
          <PARAMETER NAME="TDATA_NUM_BYTES" VALUE="4"/>
          <PARAMETER NAME="TDEST_WIDTH" VALUE="0"/>
          <PARAMETER NAME="TID_WIDTH" VALUE="0"/>
          <PARAMETER NAME="TUSER_WIDTH" VALUE="0"/>
          <PARAMETER NAME="HAS_TREADY" VALUE="0"/>
          <PARAMETER NAME="HAS_TSTRB" VALUE="0"/>
          <PARAMETER NAME="HAS_TKEEP" VALUE="0"/>
          <PARAMETER NAME="HAS_TLAST" VALUE="0"/>
          <PARAMETER NAME="FREQ_HZ" VALUE="122880000"/>
          <PARAMETER NAME="PHASE" VALUE="0.0"/>
          <PARAMETER NAME="CLK_DOMAIN" VALUE="system_pll_0_0_clk_out1"/>
          <PARAMETER NAME="LAYERED_METADATA" VALUE="xilinx.com:interface:datatypes:1.0 {TDATA {datatype {name {attribs {resolve_type immediate dependency {} format string minimum {} maximum {}} value {}} bitwidth {attribs {resolve_type automatic dependency {} format long minimum {} maximum {}} value 32} bitoffset {attribs {resolve_type immediate dependency {} format long minimum {} maximum {}} value 0} array_type {name {attribs {resolve_type immediate dependency {} format string minimum {} maximum {}} value chan} size {attribs {resolve_type generated dependency chan_size format long minimum {} maximum {}} value 1} stride {attribs {resolve_type generated dependency chan_stride format long minimum {} maximum {}} value 32} datatype {name {attribs {resolve_type immediate dependency {} format string minimum {} maximum {}} value {}} bitwidth {attribs {resolve_type generated dependency data_width format long minimum {} maximum {}} value 32} bitoffset {attribs {resolve_type immediate dependency {} format long minimum {} maximum {}} value 0} real {fixed {fractwidth {attribs {resolve_type generated dependency data_fractwidth format long minimum {} maximum {}} value 0} signed {attribs {resolve_type immediate dependency {} format bool minimum {} maximum {}} value true}}}}}}} TDATA_WIDTH 32 TUSER {datatype {name {attribs {resolve_type immediate dependency {} format string minimum {} maximum {}} value {}} bitwidth {attribs {resolve_type automatic dependency {} format long minimum {} maximum {}} value 0} bitoffset {attribs {resolve_type immediate dependency {} format long minimum {} maximum {}} value 0} struct {field_chan_out {name {attribs {resolve_type immediate dependency {} format string minimum {} maximum {}} value chan_out} enabled {attribs {resolve_type generated dependency enabled format bool minimum {} maximum {}} value false} datatype {name {attribs {resolve_type immediate dependency {} format string minimum {} maximum {}} value {}} bitwidth {attribs {resolve_type generated dependency chan_out_width format long minimum {} maximum {}} value 0} bitoffset {attribs {resolve_type immediate dependency {} format long minimum {} maximum {}} value 0} integer {signed {attribs {resolve_type immediate dependency {} format bool minimum {} maximum {}} value false}}}} field_chan_sync {name {attribs {resolve_type immediate dependency {} format string minimum {} maximum {}} value chan_sync} enabled {attribs {resolve_type generated dependency enabled format bool minimum {} maximum {}} value false} datatype {name {attribs {resolve_type immediate dependency {} format string minimum {} maximum {}} value {}} bitwidth {attribs {resolve_type generated dependency chan_sync_width format long minimum {} maximum {}} value 0} bitoffset {attribs {resolve_type generated dependency chan_sync_offset format long minimum {} maximum {}} value 0}}}}}} TUSER_WIDTH 0}"/>
          <PARAMETER NAME="INSERT_VIP" VALUE="0"/>
          <PORTMAPS>
            <PORTMAP LOGICAL="TDATA" PHYSICAL="m_axis_data_tdata"/>
            <PORTMAP LOGICAL="TVALID" PHYSICAL="m_axis_data_tvalid"/>
          </PORTMAPS>
        </BUSINTERFACE>
        <BUSINTERFACE BUSNAME="rate_2_m_axis" NAME="S_AXIS_CONFIG" TYPE="TARGET" VLNV="xilinx.com:interface:axis:1.0">
          <PARAMETER NAME="TDATA_NUM_BYTES" VALUE="1"/>
          <PARAMETER NAME="TDEST_WIDTH" VALUE="0"/>
          <PARAMETER NAME="TID_WIDTH" VALUE="0"/>
          <PARAMETER NAME="TUSER_WIDTH" VALUE="0"/>
          <PARAMETER NAME="HAS_TREADY" VALUE="1"/>
          <PARAMETER NAME="HAS_TSTRB" VALUE="0"/>
          <PARAMETER NAME="HAS_TKEEP" VALUE="0"/>
          <PARAMETER NAME="HAS_TLAST" VALUE="0"/>
          <PARAMETER NAME="FREQ_HZ" VALUE="122880000"/>
          <PARAMETER NAME="PHASE" VALUE="0.0"/>
          <PARAMETER NAME="CLK_DOMAIN" VALUE="system_pll_0_0_clk_out1"/>
          <PARAMETER NAME="LAYERED_METADATA" VALUE="undef"/>
          <PARAMETER NAME="INSERT_VIP" VALUE="0"/>
          <PORTMAPS>
            <PORTMAP LOGICAL="TDATA" PHYSICAL="s_axis_config_tdata"/>
            <PORTMAP LOGICAL="TREADY" PHYSICAL="s_axis_config_tready"/>
            <PORTMAP LOGICAL="TVALID" PHYSICAL="s_axis_config_tvalid"/>
          </PORTMAPS>
        </BUSINTERFACE>
      </BUSINTERFACES>
    </MODULE>
    <MODULE COREREVISION="15" FULLNAME="/cic_3" HWVERSION="4.0" INSTANCE="cic_3" IPTYPE="PERIPHERAL" IS_ENABLE="1" MODCLASS="PERIPHERAL" MODTYPE="cic_compiler" VLNV="xilinx.com:ip:cic_compiler:4.0">
      <DOCUMENTS>
        <DOCUMENT SOURCE="http://www.xilinx.com/cgi-bin/docs/ipdoc?c=cic_compiler;v=v4_0;d=pg140-cic-compiler.pdf"/>
      </DOCUMENTS>
      <PARAMETERS>
        <PARAMETER NAME="C_COMPONENT_NAME" VALUE="system_cic_3_0"/>
        <PARAMETER NAME="C_FILTER_TYPE" VALUE="1"/>
        <PARAMETER NAME="C_NUM_STAGES" VALUE="6"/>
        <PARAMETER NAME="C_DIFF_DELAY" VALUE="1"/>
        <PARAMETER NAME="C_RATE" VALUE="4"/>
        <PARAMETER NAME="C_INPUT_WIDTH" VALUE="24"/>
        <PARAMETER NAME="C_OUTPUT_WIDTH" VALUE="32"/>
        <PARAMETER NAME="C_USE_DSP" VALUE="0"/>
        <PARAMETER NAME="C_HAS_ROUNDING" VALUE="0"/>
        <PARAMETER NAME="C_NUM_CHANNELS" VALUE="1"/>
        <PARAMETER NAME="C_RATE_TYPE" VALUE="1"/>
        <PARAMETER NAME="C_MIN_RATE" VALUE="4"/>
        <PARAMETER NAME="C_MAX_RATE" VALUE="64"/>
        <PARAMETER NAME="C_SAMPLE_FREQ" VALUE="1"/>
        <PARAMETER NAME="C_CLK_FREQ" VALUE="1"/>
        <PARAMETER NAME="C_USE_STREAMING_INTERFACE" VALUE="1"/>
        <PARAMETER NAME="C_FAMILY" VALUE="zynq"/>
        <PARAMETER NAME="C_XDEVICEFAMILY" VALUE="zynq"/>
        <PARAMETER NAME="C_C1" VALUE="39"/>
        <PARAMETER NAME="C_C2" VALUE="38"/>
        <PARAMETER NAME="C_C3" VALUE="37"/>
        <PARAMETER NAME="C_C4" VALUE="36"/>
        <PARAMETER NAME="C_C5" VALUE="36"/>
        <PARAMETER NAME="C_C6" VALUE="35"/>
        <PARAMETER NAME="C_I1" VALUE="60"/>
        <PARAMETER NAME="C_I2" VALUE="60"/>
        <PARAMETER NAME="C_I3" VALUE="55"/>
        <PARAMETER NAME="C_I4" VALUE="50"/>
        <PARAMETER NAME="C_I5" VALUE="46"/>
        <PARAMETER NAME="C_I6" VALUE="41"/>
        <PARAMETER NAME="C_S_AXIS_CONFIG_TDATA_WIDTH" VALUE="8"/>
        <PARAMETER NAME="C_S_AXIS_DATA_TDATA_WIDTH" VALUE="24"/>
        <PARAMETER NAME="C_M_AXIS_DATA_TDATA_WIDTH" VALUE="32"/>
        <PARAMETER NAME="C_M_AXIS_DATA_TUSER_WIDTH" VALUE="1"/>
        <PARAMETER NAME="C_HAS_DOUT_TREADY" VALUE="0"/>
        <PARAMETER NAME="C_HAS_ACLKEN" VALUE="0"/>
        <PARAMETER NAME="C_HAS_ARESETN" VALUE="1"/>
        <PARAMETER NAME="Component_Name" VALUE="system_cic_3_0"/>
        <PARAMETER NAME="GUI_Behaviour" VALUE="Coregen"/>
        <PARAMETER NAME="Filter_Type" VALUE="Decimation"/>
        <PARAMETER NAME="Number_Of_Stages" VALUE="6"/>
        <PARAMETER NAME="Differential_Delay" VALUE="1"/>
        <PARAMETER NAME="Number_Of_Channels" VALUE="1"/>
        <PARAMETER NAME="Sample_Rate_Changes" VALUE="Programmable"/>
        <PARAMETER NAME="Fixed_Or_Initial_Rate" VALUE="4"/>
        <PARAMETER NAME="Minimum_Rate" VALUE="4"/>
        <PARAMETER NAME="Maximum_Rate" VALUE="64"/>
        <PARAMETER NAME="RateSpecification" VALUE="Frequency_Specification"/>
        <PARAMETER NAME="Input_Sample_Frequency" VALUE="122.88"/>
        <PARAMETER NAME="Clock_Frequency" VALUE="122.88"/>
        <PARAMETER NAME="HardwareOversamplingRate" VALUE="1"/>
        <PARAMETER NAME="SamplePeriod" VALUE="1"/>
        <PARAMETER NAME="Response_Magnitude" VALUE="Normalized"/>
        <PARAMETER NAME="Passband_Min" VALUE="0.0"/>
        <PARAMETER NAME="Stopband_Min" VALUE="0.5"/>
        <PARAMETER NAME="Passband_Max" VALUE="0.5"/>
        <PARAMETER NAME="Stopband_Max" VALUE="1.0"/>
        <PARAMETER NAME="Input_Data_Width" VALUE="24"/>
        <PARAMETER NAME="Quantization" VALUE="Truncation"/>
        <PARAMETER NAME="Output_Data_Width" VALUE="32"/>
        <PARAMETER NAME="Use_Xtreme_DSP_Slice" VALUE="false"/>
        <PARAMETER NAME="Use_Streaming_Interface" VALUE="true"/>
        <PARAMETER NAME="HAS_ACLKEN" VALUE="false"/>
        <PARAMETER NAME="HAS_ARESETN" VALUE="true"/>
        <PARAMETER NAME="HAS_DOUT_TREADY" VALUE="false"/>
        <PARAMETER NAME="EDK_IPTYPE" VALUE="PERIPHERAL"/>
      </PARAMETERS>
      <PORTS>
        <PORT CLKFREQUENCY="122880000" DIR="I" NAME="aclk" SIGIS="clk" SIGNAME="pll_0_clk_out1">
          <CONNECTIONS>
            <CONNECTION INSTANCE="pll_0" PORT="clk_out1"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" NAME="aresetn" POLARITY="ACTIVE_LOW" SIGIS="rst" SIGNAME="slice_0_dout">
          <CONNECTIONS>
            <CONNECTION INSTANCE="slice_0" PORT="dout"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" LEFT="7" NAME="s_axis_config_tdata" RIGHT="0" SIGIS="undef" SIGNAME="cic_3_s_axis_config_tdata">
          <CONNECTIONS>
            <CONNECTION INSTANCE="rate_3" PORT="m_axis_tdata"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" NAME="s_axis_config_tvalid" SIGIS="undef" SIGNAME="cic_3_s_axis_config_tvalid">
          <CONNECTIONS>
            <CONNECTION INSTANCE="rate_3" PORT="m_axis_tvalid"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" NAME="s_axis_config_tready" SIGIS="undef" SIGNAME="cic_3_s_axis_config_tready">
          <CONNECTIONS>
            <CONNECTION INSTANCE="rate_3" PORT="m_axis_tready"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" LEFT="23" NAME="s_axis_data_tdata" RIGHT="0" SIGIS="undef" SIGNAME="mult_3_P">
          <CONNECTIONS>
            <CONNECTION INSTANCE="mult_3" PORT="P"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" NAME="s_axis_data_tvalid" SIGIS="undef" SIGNAME="const_0_dout">
          <CONNECTIONS>
            <CONNECTION INSTANCE="const_0" PORT="dout"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" NAME="s_axis_data_tready" SIGIS="undef"/>
        <PORT DIR="O" LEFT="31" NAME="m_axis_data_tdata" RIGHT="0" SIGIS="undef" SIGNAME="cic_3_m_axis_data_tdata">
          <CONNECTIONS>
            <CONNECTION INSTANCE="comb_0" PORT="s_axis_tdata"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" NAME="m_axis_data_tvalid" SIGIS="undef" SIGNAME="cic_3_m_axis_data_tvalid">
          <CONNECTIONS>
            <CONNECTION INSTANCE="comb_0" PORT="s_axis_tvalid"/>
          </CONNECTIONS>
        </PORT>
      </PORTS>
      <BUSINTERFACES>
        <BUSINTERFACE BUSNAME="__NOC__" NAME="S_AXIS_DATA" TYPE="TARGET" VLNV="xilinx.com:interface:axis:1.0">
          <PARAMETER NAME="TDATA_NUM_BYTES" VALUE="3"/>
          <PARAMETER NAME="TDEST_WIDTH" VALUE="0"/>
          <PARAMETER NAME="TID_WIDTH" VALUE="0"/>
          <PARAMETER NAME="TUSER_WIDTH" VALUE="0"/>
          <PARAMETER NAME="HAS_TREADY" VALUE="1"/>
          <PARAMETER NAME="HAS_TSTRB" VALUE="0"/>
          <PARAMETER NAME="HAS_TKEEP" VALUE="0"/>
          <PARAMETER NAME="HAS_TLAST" VALUE="0"/>
          <PARAMETER NAME="FREQ_HZ" VALUE="122880000"/>
          <PARAMETER NAME="PHASE" VALUE="0.0"/>
          <PARAMETER NAME="CLK_DOMAIN" VALUE="system_pll_0_0_clk_out1"/>
          <PARAMETER NAME="LAYERED_METADATA" VALUE="undef"/>
          <PARAMETER NAME="INSERT_VIP" VALUE="0"/>
          <PORTMAPS>
            <PORTMAP LOGICAL="TDATA" PHYSICAL="s_axis_data_tdata"/>
            <PORTMAP LOGICAL="TREADY" PHYSICAL="s_axis_data_tready"/>
            <PORTMAP LOGICAL="TVALID" PHYSICAL="s_axis_data_tvalid"/>
          </PORTMAPS>
        </BUSINTERFACE>
        <BUSINTERFACE BUSNAME="cic_3_M_AXIS_DATA" NAME="M_AXIS_DATA" TYPE="INITIATOR" VLNV="xilinx.com:interface:axis:1.0">
          <PARAMETER NAME="TDATA_NUM_BYTES" VALUE="4"/>
          <PARAMETER NAME="TDEST_WIDTH" VALUE="0"/>
          <PARAMETER NAME="TID_WIDTH" VALUE="0"/>
          <PARAMETER NAME="TUSER_WIDTH" VALUE="0"/>
          <PARAMETER NAME="HAS_TREADY" VALUE="0"/>
          <PARAMETER NAME="HAS_TSTRB" VALUE="0"/>
          <PARAMETER NAME="HAS_TKEEP" VALUE="0"/>
          <PARAMETER NAME="HAS_TLAST" VALUE="0"/>
          <PARAMETER NAME="FREQ_HZ" VALUE="122880000"/>
          <PARAMETER NAME="PHASE" VALUE="0.0"/>
          <PARAMETER NAME="CLK_DOMAIN" VALUE="system_pll_0_0_clk_out1"/>
          <PARAMETER NAME="LAYERED_METADATA" VALUE="xilinx.com:interface:datatypes:1.0 {TDATA {datatype {name {attribs {resolve_type immediate dependency {} format string minimum {} maximum {}} value {}} bitwidth {attribs {resolve_type automatic dependency {} format long minimum {} maximum {}} value 32} bitoffset {attribs {resolve_type immediate dependency {} format long minimum {} maximum {}} value 0} array_type {name {attribs {resolve_type immediate dependency {} format string minimum {} maximum {}} value chan} size {attribs {resolve_type generated dependency chan_size format long minimum {} maximum {}} value 1} stride {attribs {resolve_type generated dependency chan_stride format long minimum {} maximum {}} value 32} datatype {name {attribs {resolve_type immediate dependency {} format string minimum {} maximum {}} value {}} bitwidth {attribs {resolve_type generated dependency data_width format long minimum {} maximum {}} value 32} bitoffset {attribs {resolve_type immediate dependency {} format long minimum {} maximum {}} value 0} real {fixed {fractwidth {attribs {resolve_type generated dependency data_fractwidth format long minimum {} maximum {}} value 0} signed {attribs {resolve_type immediate dependency {} format bool minimum {} maximum {}} value true}}}}}}} TDATA_WIDTH 32 TUSER {datatype {name {attribs {resolve_type immediate dependency {} format string minimum {} maximum {}} value {}} bitwidth {attribs {resolve_type automatic dependency {} format long minimum {} maximum {}} value 0} bitoffset {attribs {resolve_type immediate dependency {} format long minimum {} maximum {}} value 0} struct {field_chan_out {name {attribs {resolve_type immediate dependency {} format string minimum {} maximum {}} value chan_out} enabled {attribs {resolve_type generated dependency enabled format bool minimum {} maximum {}} value false} datatype {name {attribs {resolve_type immediate dependency {} format string minimum {} maximum {}} value {}} bitwidth {attribs {resolve_type generated dependency chan_out_width format long minimum {} maximum {}} value 0} bitoffset {attribs {resolve_type immediate dependency {} format long minimum {} maximum {}} value 0} integer {signed {attribs {resolve_type immediate dependency {} format bool minimum {} maximum {}} value false}}}} field_chan_sync {name {attribs {resolve_type immediate dependency {} format string minimum {} maximum {}} value chan_sync} enabled {attribs {resolve_type generated dependency enabled format bool minimum {} maximum {}} value false} datatype {name {attribs {resolve_type immediate dependency {} format string minimum {} maximum {}} value {}} bitwidth {attribs {resolve_type generated dependency chan_sync_width format long minimum {} maximum {}} value 0} bitoffset {attribs {resolve_type generated dependency chan_sync_offset format long minimum {} maximum {}} value 0}}}}}} TUSER_WIDTH 0}"/>
          <PARAMETER NAME="INSERT_VIP" VALUE="0"/>
          <PORTMAPS>
            <PORTMAP LOGICAL="TDATA" PHYSICAL="m_axis_data_tdata"/>
            <PORTMAP LOGICAL="TVALID" PHYSICAL="m_axis_data_tvalid"/>
          </PORTMAPS>
        </BUSINTERFACE>
        <BUSINTERFACE BUSNAME="rate_3_m_axis" NAME="S_AXIS_CONFIG" TYPE="TARGET" VLNV="xilinx.com:interface:axis:1.0">
          <PARAMETER NAME="TDATA_NUM_BYTES" VALUE="1"/>
          <PARAMETER NAME="TDEST_WIDTH" VALUE="0"/>
          <PARAMETER NAME="TID_WIDTH" VALUE="0"/>
          <PARAMETER NAME="TUSER_WIDTH" VALUE="0"/>
          <PARAMETER NAME="HAS_TREADY" VALUE="1"/>
          <PARAMETER NAME="HAS_TSTRB" VALUE="0"/>
          <PARAMETER NAME="HAS_TKEEP" VALUE="0"/>
          <PARAMETER NAME="HAS_TLAST" VALUE="0"/>
          <PARAMETER NAME="FREQ_HZ" VALUE="122880000"/>
          <PARAMETER NAME="PHASE" VALUE="0.0"/>
          <PARAMETER NAME="CLK_DOMAIN" VALUE="system_pll_0_0_clk_out1"/>
          <PARAMETER NAME="LAYERED_METADATA" VALUE="undef"/>
          <PARAMETER NAME="INSERT_VIP" VALUE="0"/>
          <PORTMAPS>
            <PORTMAP LOGICAL="TDATA" PHYSICAL="s_axis_config_tdata"/>
            <PORTMAP LOGICAL="TREADY" PHYSICAL="s_axis_config_tready"/>
            <PORTMAP LOGICAL="TVALID" PHYSICAL="s_axis_config_tvalid"/>
          </PORTMAPS>
        </BUSINTERFACE>
      </BUSINTERFACES>
    </MODULE>
    <MODULE COREREVISION="23" FULLNAME="/comb_0" HWVERSION="1.1" INSTANCE="comb_0" IPTYPE="BUS" IS_ENABLE="1" MODCLASS="BUS" MODTYPE="axis_combiner" VLNV="xilinx.com:ip:axis_combiner:1.1">
      <DOCUMENTS>
        <DOCUMENT SOURCE="https://www.xilinx.com/cgi-bin/docs/ipdoc?c=axis_combiner;v=v1_1;d=pg085-axi4stream-infrastructure.pdf"/>
      </DOCUMENTS>
      <PARAMETERS>
        <PARAMETER NAME="C_FAMILY" VALUE="zynq"/>
        <PARAMETER NAME="C_AXIS_TDATA_WIDTH" VALUE="32"/>
        <PARAMETER NAME="C_AXIS_TID_WIDTH" VALUE="1"/>
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        <PARAMETER NAME="IN107_WIDTH" VALUE="1"/>
        <PARAMETER NAME="IN108_WIDTH" VALUE="1"/>
        <PARAMETER NAME="IN109_WIDTH" VALUE="1"/>
        <PARAMETER NAME="IN110_WIDTH" VALUE="1"/>
        <PARAMETER NAME="IN111_WIDTH" VALUE="1"/>
        <PARAMETER NAME="IN112_WIDTH" VALUE="1"/>
        <PARAMETER NAME="IN113_WIDTH" VALUE="1"/>
        <PARAMETER NAME="IN114_WIDTH" VALUE="1"/>
        <PARAMETER NAME="IN115_WIDTH" VALUE="1"/>
        <PARAMETER NAME="IN116_WIDTH" VALUE="1"/>
        <PARAMETER NAME="IN117_WIDTH" VALUE="1"/>
        <PARAMETER NAME="IN118_WIDTH" VALUE="1"/>
        <PARAMETER NAME="IN119_WIDTH" VALUE="1"/>
        <PARAMETER NAME="IN120_WIDTH" VALUE="1"/>
        <PARAMETER NAME="IN121_WIDTH" VALUE="1"/>
        <PARAMETER NAME="IN122_WIDTH" VALUE="1"/>
        <PARAMETER NAME="IN123_WIDTH" VALUE="1"/>
        <PARAMETER NAME="IN124_WIDTH" VALUE="1"/>
        <PARAMETER NAME="IN125_WIDTH" VALUE="1"/>
        <PARAMETER NAME="IN126_WIDTH" VALUE="1"/>
        <PARAMETER NAME="IN127_WIDTH" VALUE="1"/>
        <PARAMETER NAME="dout_width" VALUE="32"/>
        <PARAMETER NAME="NUM_PORTS" VALUE="2"/>
        <PARAMETER NAME="Component_Name" VALUE="system_concat_0_0"/>
        <PARAMETER NAME="EDK_IPTYPE" VALUE="PERIPHERAL"/>
      </PARAMETERS>
      <PORTS>
        <PORT DIR="I" LEFT="15" NAME="In0" RIGHT="0" SIGIS="undef" SIGNAME="mult_4_P">
          <CONNECTIONS>
            <CONNECTION INSTANCE="mult_4" PORT="P"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" LEFT="15" NAME="In1" RIGHT="0" SIGIS="undef" SIGNAME="mult_5_P">
          <CONNECTIONS>
            <CONNECTION INSTANCE="mult_5" PORT="P"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" LEFT="31" NAME="dout" RIGHT="0" SIGIS="undef" SIGNAME="concat_0_dout">
          <CONNECTIONS>
            <CONNECTION INSTANCE="dac_0" PORT="s_axis_tdata"/>
          </CONNECTIONS>
        </PORT>
      </PORTS>
      <BUSINTERFACES/>
    </MODULE>
    <MODULE COREREVISION="7" FULLNAME="/const_0" HWVERSION="1.1" INSTANCE="const_0" IPTYPE="PERIPHERAL" IS_ENABLE="1" MODCLASS="PERIPHERAL" MODTYPE="xlconstant" VLNV="xilinx.com:ip:xlconstant:1.1">
      <DOCUMENTS/>
      <PARAMETERS>
        <PARAMETER NAME="CONST_WIDTH" VALUE="1"/>
        <PARAMETER NAME="CONST_VAL" VALUE="0x1"/>
        <PARAMETER NAME="Component_Name" VALUE="system_const_0_0"/>
        <PARAMETER NAME="EDK_IPTYPE" VALUE="PERIPHERAL"/>
      </PARAMETERS>
      <PORTS>
        <PORT DIR="O" LEFT="0" NAME="dout" RIGHT="0" SIGIS="undef" SIGNAME="const_0_dout">
          <CONNECTIONS>
            <CONNECTION INSTANCE="rst_0" PORT="ext_reset_in"/>
            <CONNECTION INSTANCE="dac_0" PORT="s_axis_tvalid"/>
            <CONNECTION INSTANCE="cic_0" PORT="s_axis_data_tvalid"/>
            <CONNECTION INSTANCE="cic_1" PORT="s_axis_data_tvalid"/>
            <CONNECTION INSTANCE="cic_2" PORT="s_axis_data_tvalid"/>
            <CONNECTION INSTANCE="cic_3" PORT="s_axis_data_tvalid"/>
          </CONNECTIONS>
        </PORT>
      </PORTS>
      <BUSINTERFACES/>
    </MODULE>
    <MODULE COREREVISION="7" FULLNAME="/const_GPIO_out" HWVERSION="1.1" INSTANCE="const_GPIO_out" IPTYPE="PERIPHERAL" IS_ENABLE="1" MODCLASS="PERIPHERAL" MODTYPE="xlconstant" VLNV="xilinx.com:ip:xlconstant:1.1">
      <DOCUMENTS/>
      <PARAMETERS>
        <PARAMETER NAME="CONST_WIDTH" VALUE="8"/>
        <PARAMETER NAME="CONST_VAL" VALUE="0x00"/>
        <PARAMETER NAME="Component_Name" VALUE="system_const_GPIO_out_0"/>
        <PARAMETER NAME="EDK_IPTYPE" VALUE="PERIPHERAL"/>
      </PARAMETERS>
      <PORTS>
        <PORT DIR="O" LEFT="7" NAME="dout" RIGHT="0" SIGIS="undef" SIGNAME="const_GPIO_out_dout">
          <CONNECTIONS>
            <CONNECTION INSTANCE="io_bridge_out" PORT="dir"/>
          </CONNECTIONS>
        </PORT>
      </PORTS>
      <BUSINTERFACES/>
    </MODULE>
    <MODULE COREREVISION="7" FULLNAME="/const_GPIO_out1" HWVERSION="1.1" INSTANCE="const_GPIO_out1" IPTYPE="PERIPHERAL" IS_ENABLE="1" MODCLASS="PERIPHERAL" MODTYPE="xlconstant" VLNV="xilinx.com:ip:xlconstant:1.1">
      <DOCUMENTS/>
      <PARAMETERS>
        <PARAMETER NAME="CONST_WIDTH" VALUE="1"/>
        <PARAMETER NAME="CONST_VAL" VALUE="0x1"/>
        <PARAMETER NAME="Component_Name" VALUE="system_const_GPIO_out_2"/>
        <PARAMETER NAME="EDK_IPTYPE" VALUE="PERIPHERAL"/>
      </PARAMETERS>
      <PORTS>
        <PORT DIR="O" LEFT="0" NAME="dout" RIGHT="0" SIGIS="undef" SIGNAME="const_GPIO_out1_dout">
          <CONNECTIONS>
            <CONNECTION INSTANCE="fsk_detector_1_00_0" PORT="out_ready"/>
          </CONNECTIONS>
        </PORT>
      </PORTS>
      <BUSINTERFACES/>
    </MODULE>
    <MODULE COREREVISION="1" FULLNAME="/dac_0" HWVERSION="1.0" INSTANCE="dac_0" IPTYPE="PERIPHERAL" IS_ENABLE="1" MODCLASS="PERIPHERAL" MODTYPE="axis_red_pitaya_dac" VLNV="pavel-demin:user:axis_red_pitaya_dac:1.0">
      <DOCUMENTS/>
      <PARAMETERS>
        <PARAMETER NAME="DAC_DATA_WIDTH" VALUE="14"/>
        <PARAMETER NAME="AXIS_TDATA_WIDTH" VALUE="32"/>
        <PARAMETER NAME="Component_Name" VALUE="system_dac_0_0"/>
        <PARAMETER NAME="EDK_IPTYPE" VALUE="PERIPHERAL"/>
      </PARAMETERS>
      <PORTS>
        <PORT CLKFREQUENCY="122880000" DIR="I" NAME="aclk" SIGIS="clk" SIGNAME="pll_0_clk_out1">
          <CONNECTIONS>
            <CONNECTION INSTANCE="pll_0" PORT="clk_out1"/>
          </CONNECTIONS>
        </PORT>
        <PORT CLKFREQUENCY="245760000" DIR="I" NAME="ddr_clk" SIGIS="clk" SIGNAME="pll_0_clk_out2">
          <CONNECTIONS>
            <CONNECTION INSTANCE="pll_0" PORT="clk_out2"/>
          </CONNECTIONS>
        </PORT>
        <PORT CLKFREQUENCY="245760000" DIR="I" NAME="wrt_clk" SIGIS="clk" SIGNAME="pll_0_clk_out3">
          <CONNECTIONS>
            <CONNECTION INSTANCE="pll_0" PORT="clk_out3"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" NAME="locked" SIGIS="undef" SIGNAME="pll_0_locked">
          <CONNECTIONS>
            <CONNECTION INSTANCE="pll_0" PORT="locked"/>
          </CONNECTIONS>
        </PORT>
        <PORT CLKFREQUENCY="100000000" DIR="O" NAME="dac_clk" SIGIS="clk" SIGNAME="dac_0_dac_clk">
          <CONNECTIONS>
            <CONNECTION INSTANCE="External_Ports" PORT="dac_clk_o"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" NAME="dac_rst" POLARITY="ACTIVE_LOW" SIGIS="rst" SIGNAME="dac_0_dac_rst">
          <CONNECTIONS>
            <CONNECTION INSTANCE="External_Ports" PORT="dac_rst_o"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" NAME="dac_sel" SIGIS="undef" SIGNAME="dac_0_dac_sel">
          <CONNECTIONS>
            <CONNECTION INSTANCE="External_Ports" PORT="dac_sel_o"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" NAME="dac_wrt" SIGIS="undef" SIGNAME="dac_0_dac_wrt">
          <CONNECTIONS>
            <CONNECTION INSTANCE="External_Ports" PORT="dac_wrt_o"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" LEFT="13" NAME="dac_dat" RIGHT="0" SIGIS="undef" SIGNAME="dac_0_dac_dat">
          <CONNECTIONS>
            <CONNECTION INSTANCE="External_Ports" PORT="dac_dat_o"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" NAME="s_axis_tready" SIGIS="undef"/>
        <PORT DIR="I" LEFT="31" NAME="s_axis_tdata" RIGHT="0" SIGIS="undef" SIGNAME="concat_0_dout">
          <CONNECTIONS>
            <CONNECTION INSTANCE="concat_0" PORT="dout"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" NAME="s_axis_tvalid" SIGIS="undef" SIGNAME="const_0_dout">
          <CONNECTIONS>
            <CONNECTION INSTANCE="const_0" PORT="dout"/>
          </CONNECTIONS>
        </PORT>
      </PORTS>
      <BUSINTERFACES>
        <BUSINTERFACE BUSNAME="__NOC__" NAME="s_axis" TYPE="TARGET" VLNV="xilinx.com:interface:axis:1.0">
          <PARAMETER NAME="TDATA_NUM_BYTES" VALUE="4"/>
          <PARAMETER NAME="TDEST_WIDTH" VALUE="0"/>
          <PARAMETER NAME="TID_WIDTH" VALUE="0"/>
          <PARAMETER NAME="TUSER_WIDTH" VALUE="0"/>
          <PARAMETER NAME="HAS_TREADY" VALUE="1"/>
          <PARAMETER NAME="HAS_TSTRB" VALUE="0"/>
          <PARAMETER NAME="HAS_TKEEP" VALUE="0"/>
          <PARAMETER NAME="HAS_TLAST" VALUE="0"/>
          <PARAMETER NAME="FREQ_HZ" VALUE="122880000"/>
          <PARAMETER NAME="PHASE" VALUE="0.0"/>
          <PARAMETER NAME="CLK_DOMAIN" VALUE="system_pll_0_0_clk_out1"/>
          <PARAMETER NAME="LAYERED_METADATA" VALUE="undef"/>
          <PARAMETER NAME="INSERT_VIP" VALUE="0"/>
          <PORTMAPS>
            <PORTMAP LOGICAL="TDATA" PHYSICAL="s_axis_tdata"/>
            <PORTMAP LOGICAL="TVALID" PHYSICAL="s_axis_tvalid"/>
            <PORTMAP LOGICAL="TREADY" PHYSICAL="s_axis_tready"/>
          </PORTMAPS>
        </BUSINTERFACE>
      </BUSINTERFACES>
    </MODULE>
    <MODULE COREREVISION="1" FULLNAME="/dds_0" HWVERSION="1.0" INSTANCE="dds_0" IPTYPE="PERIPHERAL" IS_ENABLE="1" MODCLASS="PERIPHERAL" MODTYPE="dds" VLNV="pavel-demin:user:dds:1.0">
      <DOCUMENTS/>
      <PARAMETERS>
        <PARAMETER NAME="NEGATIVE_SINE" VALUE="TRUE"/>
        <PARAMETER NAME="Component_Name" VALUE="system_dds_0_0"/>
        <PARAMETER NAME="EDK_IPTYPE" VALUE="PERIPHERAL"/>
      </PARAMETERS>
      <PORTS>
        <PORT CLKFREQUENCY="122880000" DIR="I" NAME="aclk" SIGIS="clk" SIGNAME="pll_0_clk_out1">
          <CONNECTIONS>
            <CONNECTION INSTANCE="pll_0" PORT="clk_out1"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" NAME="aresetn" POLARITY="ACTIVE_LOW" SIGIS="rst" SIGNAME="rst_0_peripheral_aresetn">
          <CONNECTIONS>
            <CONNECTION INSTANCE="rst_0" PORT="peripheral_aresetn"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" LEFT="31" NAME="pinc" RIGHT="0" SIGIS="undef" SIGNAME="slice_4_dout">
          <CONNECTIONS>
            <CONNECTION INSTANCE="slice_4" PORT="dout"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" LEFT="47" NAME="dout" RIGHT="0" SIGIS="undef" SIGNAME="dds_0_dout">
          <CONNECTIONS>
            <CONNECTION INSTANCE="dds_slice_0" PORT="din"/>
            <CONNECTION INSTANCE="dds_slice_1" PORT="din"/>
          </CONNECTIONS>
        </PORT>
      </PORTS>
      <BUSINTERFACES/>
    </MODULE>
    <MODULE COREREVISION="1" FULLNAME="/dds_1" HWVERSION="1.0" INSTANCE="dds_1" IPTYPE="PERIPHERAL" IS_ENABLE="1" MODCLASS="PERIPHERAL" MODTYPE="dds" VLNV="pavel-demin:user:dds:1.0">
      <DOCUMENTS/>
      <PARAMETERS>
        <PARAMETER NAME="NEGATIVE_SINE" VALUE="TRUE"/>
        <PARAMETER NAME="Component_Name" VALUE="system_dds_1_0"/>
        <PARAMETER NAME="EDK_IPTYPE" VALUE="PERIPHERAL"/>
      </PARAMETERS>
      <PORTS>
        <PORT CLKFREQUENCY="122880000" DIR="I" NAME="aclk" SIGIS="clk" SIGNAME="pll_0_clk_out1">
          <CONNECTIONS>
            <CONNECTION INSTANCE="pll_0" PORT="clk_out1"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" NAME="aresetn" POLARITY="ACTIVE_LOW" SIGIS="rst" SIGNAME="rst_0_peripheral_aresetn">
          <CONNECTIONS>
            <CONNECTION INSTANCE="rst_0" PORT="peripheral_aresetn"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" LEFT="31" NAME="pinc" RIGHT="0" SIGIS="undef" SIGNAME="slice_5_dout">
          <CONNECTIONS>
            <CONNECTION INSTANCE="slice_5" PORT="dout"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" LEFT="47" NAME="dout" RIGHT="0" SIGIS="undef" SIGNAME="dds_1_dout">
          <CONNECTIONS>
            <CONNECTION INSTANCE="dds_slice_2" PORT="din"/>
            <CONNECTION INSTANCE="dds_slice_3" PORT="din"/>
          </CONNECTIONS>
        </PORT>
      </PORTS>
      <BUSINTERFACES/>
    </MODULE>
    <MODULE COREREVISION="1" FULLNAME="/dds_2" HWVERSION="1.0" INSTANCE="dds_2" IPTYPE="PERIPHERAL" IS_ENABLE="1" MODCLASS="PERIPHERAL" MODTYPE="dds" VLNV="pavel-demin:user:dds:1.0">
      <DOCUMENTS/>
      <PARAMETERS>
        <PARAMETER NAME="NEGATIVE_SINE" VALUE="TRUE"/>
        <PARAMETER NAME="Component_Name" VALUE="system_dds_2_0"/>
        <PARAMETER NAME="EDK_IPTYPE" VALUE="PERIPHERAL"/>
      </PARAMETERS>
      <PORTS>
        <PORT CLKFREQUENCY="122880000" DIR="I" NAME="aclk" SIGIS="clk" SIGNAME="pll_0_clk_out1">
          <CONNECTIONS>
            <CONNECTION INSTANCE="pll_0" PORT="clk_out1"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" NAME="aresetn" POLARITY="ACTIVE_LOW" SIGIS="rst" SIGNAME="rst_0_peripheral_aresetn">
          <CONNECTIONS>
            <CONNECTION INSTANCE="rst_0" PORT="peripheral_aresetn"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" LEFT="31" NAME="pinc" RIGHT="0" SIGIS="undef" SIGNAME="slice_6_dout">
          <CONNECTIONS>
            <CONNECTION INSTANCE="slice_6" PORT="dout"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" LEFT="47" NAME="dout" RIGHT="0" SIGIS="undef" SIGNAME="dds_2_dout">
          <CONNECTIONS>
            <CONNECTION INSTANCE="mult_4" PORT="A"/>
          </CONNECTIONS>
        </PORT>
      </PORTS>
      <BUSINTERFACES/>
    </MODULE>
    <MODULE COREREVISION="1" FULLNAME="/dds_3" HWVERSION="1.0" INSTANCE="dds_3" IPTYPE="PERIPHERAL" IS_ENABLE="1" MODCLASS="PERIPHERAL" MODTYPE="dds" VLNV="pavel-demin:user:dds:1.0">
      <DOCUMENTS/>
      <PARAMETERS>
        <PARAMETER NAME="NEGATIVE_SINE" VALUE="TRUE"/>
        <PARAMETER NAME="Component_Name" VALUE="system_dds_3_0"/>
        <PARAMETER NAME="EDK_IPTYPE" VALUE="PERIPHERAL"/>
      </PARAMETERS>
      <PORTS>
        <PORT CLKFREQUENCY="122880000" DIR="I" NAME="aclk" SIGIS="clk" SIGNAME="pll_0_clk_out1">
          <CONNECTIONS>
            <CONNECTION INSTANCE="pll_0" PORT="clk_out1"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" NAME="aresetn" POLARITY="ACTIVE_LOW" SIGIS="rst" SIGNAME="rst_0_peripheral_aresetn">
          <CONNECTIONS>
            <CONNECTION INSTANCE="rst_0" PORT="peripheral_aresetn"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" LEFT="31" NAME="pinc" RIGHT="0" SIGIS="undef" SIGNAME="slice_7_dout">
          <CONNECTIONS>
            <CONNECTION INSTANCE="slice_7" PORT="dout"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" LEFT="47" NAME="dout" RIGHT="0" SIGIS="undef" SIGNAME="dds_3_dout">
          <CONNECTIONS>
            <CONNECTION INSTANCE="mult_5" PORT="A"/>
            <CONNECTION INSTANCE="mult_5" PORT="B"/>
          </CONNECTIONS>
        </PORT>
      </PORTS>
      <BUSINTERFACES/>
    </MODULE>
    <MODULE COREREVISION="1" FULLNAME="/dds_slice_0" HWVERSION="1.0" INSTANCE="dds_slice_0" IPTYPE="PERIPHERAL" IS_ENABLE="1" MODCLASS="PERIPHERAL" MODTYPE="port_slicer" VLNV="pavel-demin:user:port_slicer:1.0">
      <DOCUMENTS/>
      <PARAMETERS>
        <PARAMETER NAME="DIN_WIDTH" VALUE="48"/>
        <PARAMETER NAME="DIN_FROM" VALUE="23"/>
        <PARAMETER NAME="DIN_TO" VALUE="0"/>
        <PARAMETER NAME="Component_Name" VALUE="system_dds_slice_0_0"/>
        <PARAMETER NAME="EDK_IPTYPE" VALUE="PERIPHERAL"/>
      </PARAMETERS>
      <PORTS>
        <PORT DIR="I" LEFT="47" NAME="din" RIGHT="0" SIGIS="undef" SIGNAME="dds_0_dout">
          <CONNECTIONS>
            <CONNECTION INSTANCE="dds_0" PORT="dout"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" LEFT="23" NAME="dout" RIGHT="0" SIGIS="undef" SIGNAME="dds_slice_0_dout">
          <CONNECTIONS>
            <CONNECTION INSTANCE="mult_0" PORT="A"/>
          </CONNECTIONS>
        </PORT>
      </PORTS>
      <BUSINTERFACES/>
    </MODULE>
    <MODULE COREREVISION="1" FULLNAME="/dds_slice_1" HWVERSION="1.0" INSTANCE="dds_slice_1" IPTYPE="PERIPHERAL" IS_ENABLE="1" MODCLASS="PERIPHERAL" MODTYPE="port_slicer" VLNV="pavel-demin:user:port_slicer:1.0">
      <DOCUMENTS/>
      <PARAMETERS>
        <PARAMETER NAME="DIN_WIDTH" VALUE="48"/>
        <PARAMETER NAME="DIN_FROM" VALUE="47"/>
        <PARAMETER NAME="DIN_TO" VALUE="24"/>
        <PARAMETER NAME="Component_Name" VALUE="system_dds_slice_1_0"/>
        <PARAMETER NAME="EDK_IPTYPE" VALUE="PERIPHERAL"/>
      </PARAMETERS>
      <PORTS>
        <PORT DIR="I" LEFT="47" NAME="din" RIGHT="0" SIGIS="undef" SIGNAME="dds_0_dout">
          <CONNECTIONS>
            <CONNECTION INSTANCE="dds_0" PORT="dout"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" LEFT="23" NAME="dout" RIGHT="0" SIGIS="undef" SIGNAME="dds_slice_1_dout">
          <CONNECTIONS>
            <CONNECTION INSTANCE="mult_1" PORT="A"/>
          </CONNECTIONS>
        </PORT>
      </PORTS>
      <BUSINTERFACES/>
    </MODULE>
    <MODULE COREREVISION="1" FULLNAME="/dds_slice_2" HWVERSION="1.0" INSTANCE="dds_slice_2" IPTYPE="PERIPHERAL" IS_ENABLE="1" MODCLASS="PERIPHERAL" MODTYPE="port_slicer" VLNV="pavel-demin:user:port_slicer:1.0">
      <DOCUMENTS/>
      <PARAMETERS>
        <PARAMETER NAME="DIN_WIDTH" VALUE="48"/>
        <PARAMETER NAME="DIN_FROM" VALUE="23"/>
        <PARAMETER NAME="DIN_TO" VALUE="0"/>
        <PARAMETER NAME="Component_Name" VALUE="system_dds_slice_2_0"/>
        <PARAMETER NAME="EDK_IPTYPE" VALUE="PERIPHERAL"/>
      </PARAMETERS>
      <PORTS>
        <PORT DIR="I" LEFT="47" NAME="din" RIGHT="0" SIGIS="undef" SIGNAME="dds_1_dout">
          <CONNECTIONS>
            <CONNECTION INSTANCE="dds_1" PORT="dout"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" LEFT="23" NAME="dout" RIGHT="0" SIGIS="undef" SIGNAME="dds_slice_2_dout">
          <CONNECTIONS>
            <CONNECTION INSTANCE="mult_2" PORT="A"/>
          </CONNECTIONS>
        </PORT>
      </PORTS>
      <BUSINTERFACES/>
    </MODULE>
    <MODULE COREREVISION="1" FULLNAME="/dds_slice_3" HWVERSION="1.0" INSTANCE="dds_slice_3" IPTYPE="PERIPHERAL" IS_ENABLE="1" MODCLASS="PERIPHERAL" MODTYPE="port_slicer" VLNV="pavel-demin:user:port_slicer:1.0">
      <DOCUMENTS/>
      <PARAMETERS>
        <PARAMETER NAME="DIN_WIDTH" VALUE="48"/>
        <PARAMETER NAME="DIN_FROM" VALUE="47"/>
        <PARAMETER NAME="DIN_TO" VALUE="24"/>
        <PARAMETER NAME="Component_Name" VALUE="system_dds_slice_3_0"/>
        <PARAMETER NAME="EDK_IPTYPE" VALUE="PERIPHERAL"/>
      </PARAMETERS>
      <PORTS>
        <PORT DIR="I" LEFT="47" NAME="din" RIGHT="0" SIGIS="undef" SIGNAME="dds_1_dout">
          <CONNECTIONS>
            <CONNECTION INSTANCE="dds_1" PORT="dout"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" LEFT="23" NAME="dout" RIGHT="0" SIGIS="undef" SIGNAME="dds_slice_3_dout">
          <CONNECTIONS>
            <CONNECTION INSTANCE="mult_3" PORT="A"/>
          </CONNECTIONS>
        </PORT>
      </PORTS>
      <BUSINTERFACES/>
    </MODULE>
    <MODULE COREREVISION="17" FULLNAME="/fir_0" HWVERSION="7.2" INSTANCE="fir_0" IPTYPE="PERIPHERAL" IS_ENABLE="1" MODCLASS="PERIPHERAL" MODTYPE="fir_compiler" VLNV="xilinx.com:ip:fir_compiler:7.2">
      <DOCUMENTS>
        <DOCUMENT SOURCE="http://www.xilinx.com/cgi-bin/docs/ipdoc?c=fir_compiler;v=v7_2;d=pg149-fir-compiler.pdf"/>
      </DOCUMENTS>
      <PARAMETERS>
        <PARAMETER NAME="C_XDEVICEFAMILY" VALUE="zynq"/>
        <PARAMETER NAME="C_ELABORATION_DIR" VALUE="./"/>
        <PARAMETER NAME="C_COMPONENT_NAME" VALUE="system_fir_0_0"/>
        <PARAMETER NAME="C_COEF_FILE" VALUE="system_fir_0_0.mif"/>
        <PARAMETER NAME="C_COEF_FILE_LINES" VALUE="144"/>
        <PARAMETER NAME="C_FILTER_TYPE" VALUE="1"/>
        <PARAMETER NAME="C_INTERP_RATE" VALUE="1"/>
        <PARAMETER NAME="C_DECIM_RATE" VALUE="2"/>
        <PARAMETER NAME="C_ZERO_PACKING_FACTOR" VALUE="1"/>
        <PARAMETER NAME="C_SYMMETRY" VALUE="1"/>
        <PARAMETER NAME="C_NUM_FILTS" VALUE="1"/>
        <PARAMETER NAME="C_NUM_TAPS" VALUE="281"/>
        <PARAMETER NAME="C_NUM_CHANNELS" VALUE="1"/>
        <PARAMETER NAME="C_CHANNEL_PATTERN" VALUE="fixed"/>
        <PARAMETER NAME="C_ROUND_MODE" VALUE="4"/>
        <PARAMETER NAME="C_COEF_RELOAD" VALUE="0"/>
        <PARAMETER NAME="C_NUM_RELOAD_SLOTS" VALUE="1"/>
        <PARAMETER NAME="C_COL_MODE" VALUE="1"/>
        <PARAMETER NAME="C_COL_PIPE_LEN" VALUE="4"/>
        <PARAMETER NAME="C_COL_CONFIG" VALUE="18"/>
        <PARAMETER NAME="C_OPTIMIZATION" VALUE="0"/>
        <PARAMETER NAME="C_DATA_PATH_WIDTHS" VALUE="16,16,16,16,16,16,16,16"/>
        <PARAMETER NAME="C_DATA_IP_PATH_WIDTHS" VALUE="32,32,32,32"/>
        <PARAMETER NAME="C_DATA_PX_PATH_WIDTHS" VALUE="32,32,32,32"/>
        <PARAMETER NAME="C_DATA_WIDTH" VALUE="32"/>
        <PARAMETER NAME="C_COEF_PATH_WIDTHS" VALUE="24,24,24,24,24,24,24,24"/>
        <PARAMETER NAME="C_COEF_WIDTH" VALUE="24"/>
        <PARAMETER NAME="C_DATA_PATH_SRC" VALUE="0,1,2,3,4,5,6,7"/>
        <PARAMETER NAME="C_COEF_PATH_SRC" VALUE="0,0,0,0,0,0,0,0"/>
        <PARAMETER NAME="C_PX_PATH_SRC" VALUE="0,1,2,3,4,5,6,7"/>
        <PARAMETER NAME="C_DATA_PATH_SIGN" VALUE="1,0,1,0,1,0,1,0"/>
        <PARAMETER NAME="C_COEF_PATH_SIGN" VALUE="0,0,0,0,0,0,0,0"/>
        <PARAMETER NAME="C_ACCUM_PATH_WIDTHS" VALUE="42,41,42,41,42,41,42,41"/>
        <PARAMETER NAME="C_OUTPUT_WIDTH" VALUE="18"/>
        <PARAMETER NAME="C_OUTPUT_PATH_WIDTHS" VALUE="18,18,18,18"/>
        <PARAMETER NAME="C_ACCUM_OP_PATH_WIDTHS" VALUE="57,57,57,57"/>
        <PARAMETER NAME="C_EXT_MULT_CNFG" VALUE="0,1,0,16;2,3,0,16;4,5,0,16;6,7,0,16"/>
        <PARAMETER NAME="C_DATA_PATH_PSAMP_SRC" VALUE="0"/>
        <PARAMETER NAME="C_OP_PATH_PSAMP_SRC" VALUE="0"/>
        <PARAMETER NAME="C_NUM_MADDS" VALUE="18"/>
        <PARAMETER NAME="C_OPT_MADDS" VALUE="none"/>
        <PARAMETER NAME="C_OVERSAMPLING_RATE" VALUE="4"/>
        <PARAMETER NAME="C_INPUT_RATE" VALUE="4"/>
        <PARAMETER NAME="C_OUTPUT_RATE" VALUE="8"/>
        <PARAMETER NAME="C_DATA_MEMTYPE" VALUE="0"/>
        <PARAMETER NAME="C_COEF_MEMTYPE" VALUE="2"/>
        <PARAMETER NAME="C_IPBUFF_MEMTYPE" VALUE="2"/>
        <PARAMETER NAME="C_OPBUFF_MEMTYPE" VALUE="0"/>
        <PARAMETER NAME="C_DATAPATH_MEMTYPE" VALUE="2"/>
        <PARAMETER NAME="C_MEM_ARRANGEMENT" VALUE="1"/>
        <PARAMETER NAME="C_DATA_MEM_PACKING" VALUE="0"/>
        <PARAMETER NAME="C_COEF_MEM_PACKING" VALUE="0"/>
        <PARAMETER NAME="C_FILTS_PACKED" VALUE="0"/>
        <PARAMETER NAME="C_LATENCY" VALUE="32"/>
        <PARAMETER NAME="C_HAS_ARESETn" VALUE="1"/>
        <PARAMETER NAME="C_HAS_ACLKEN" VALUE="0"/>
        <PARAMETER NAME="C_DATA_HAS_TLAST" VALUE="0"/>
        <PARAMETER NAME="C_S_DATA_HAS_FIFO" VALUE="1"/>
        <PARAMETER NAME="C_S_DATA_HAS_TUSER" VALUE="0"/>
        <PARAMETER NAME="C_S_DATA_TDATA_WIDTH" VALUE="128"/>
        <PARAMETER NAME="C_S_DATA_TUSER_WIDTH" VALUE="1"/>
        <PARAMETER NAME="C_M_DATA_HAS_TREADY" VALUE="1"/>
        <PARAMETER NAME="C_M_DATA_HAS_TUSER" VALUE="0"/>
        <PARAMETER NAME="C_M_DATA_TDATA_WIDTH" VALUE="96"/>
        <PARAMETER NAME="C_M_DATA_TUSER_WIDTH" VALUE="1"/>
        <PARAMETER NAME="C_HAS_CONFIG_CHANNEL" VALUE="0"/>
        <PARAMETER NAME="C_CONFIG_SYNC_MODE" VALUE="0"/>
        <PARAMETER NAME="C_CONFIG_PACKET_SIZE" VALUE="0"/>
        <PARAMETER NAME="C_CONFIG_TDATA_WIDTH" VALUE="1"/>
        <PARAMETER NAME="C_RELOAD_TDATA_WIDTH" VALUE="1"/>
        <PARAMETER NAME="Component_Name" VALUE="system_fir_0_0"/>
        <PARAMETER NAME="GUI_Behaviour" VALUE="Coregen"/>
        <PARAMETER NAME="CoefficientSource" VALUE="Vector"/>
        <PARAMETER NAME="CoefficientVector" VALUE="-4.3206471974e-08, 1.9581108834e-08, 3.8109090962e-08, 1.4084131418e-09, 1.2186120186e-08, -4.3002365521e-08, -1.3853077565e-07, 1.0133745579e-07, 3.7888894052e-07, -1.6394613230e-07, -7.7661761489e-07, 2.0712149544e-07, 1.3774224210e-06, -1.9384365527e-07, -2.2249377290e-06, 7.2763377227e-08, 3.3549988889e-06, 2.2117927620e-07, -4.7889010594e-06, -7.6397724595e-07, 6.5260611238e-06, 1.6368965465e-06, -8.5375061091e-06, -2.9191987685e-06, 1.0758341788e-05, 4.6752496998e-06, -1.3084991486e-05, -6.9412383420e-06, 1.5373724961e-05, 9.7084647273e-06, -1.7443962288e-05, -1.2905490830e-05, 1.9086646276e-05, 1.6380162505e-05, -2.0078608383e-05, -1.9883422927e-05, 2.0203022903e-05, 2.3056727953e-05, -1.9275907764e-05, -2.5425425753e-05, 1.7177613167e-05, 2.6400053739e-05, -1.3887984508e-05, -2.5287767236e-05, 9.5223982251e-06, 2.1313177486e-05, -4.3728197481e-06, -1.3665196308e-05, -1.0766754409e-06, 1.5310917825e-06, 6.1157778312e-06, 1.5831781930e-05, -9.8065695691e-06, -3.9025740577e-05, 1.0994139826e-05, 6.8433254890e-05, -8.3394585095e-06, -1.0413520871e-04, 3.7650515294e-07, 1.4583183818e-04, 1.4403443484e-05, -1.9277411182e-04, -3.7440682291e-05, 2.4371243539e-04, 6.9969543240e-05, -2.9687173927e-04, -1.1285857228e-04, 3.4996062912e-04, 1.6643173499e-04, -4.0023458429e-04, -2.3031764274e-04, 4.4453252714e-04, 3.0318466104e-04, -4.7951215941e-04, -3.8264756455e-04, 5.0179308310e-04, 4.6508817914e-04, -5.0822117940e-04, -5.4554763871e-04, 4.9616951008e-04, 6.1766717590e-04, -4.6388070868e-04, -6.7369245331e-04, 4.1083915738e-04, 7.0454923950e-04, -3.3816268708e-04, -6.9999979578e-04, 2.4899722791e-04, 6.4888144112e-04, -1.4890118284e-04, -5.3942758146e-04, 4.6206061884e-05, 3.5965967563e-04, 4.7605082323e-05, -9.8021126546e-05, -1.1791553911e-04, -2.5647044402e-04, 1.4635687092e-04, 7.1327754530e-04, -1.1093829736e-04, -1.2799048805e-03, -1.4106495666e-05, 1.9613024094e-03, 2.5839388583e-04, -2.7593013177e-03, -6.5548048055e-04, 3.6720962046e-03, 1.2430372921e-03, -4.6937909542e-03, -2.0632159584e-03, 5.8140101675e-03, 3.1633610776e-03, -7.0175713933e-03, -4.5973156063e-03, 8.2841916600e-03, 6.4277320980e-03, -9.5881685667e-03, -8.7303353142e-03, 1.0896800128e-02, 1.1598799243e-02, -1.2171477770e-02, -1.5158439259e-02, 1.3362938210e-02, 1.9583979076e-02, -1.4406996028e-02, -2.5135038845e-02, 1.5213119554e-02, 3.2223155290e-02, -1.5638192699e-02, -4.1549149361e-02, 1.5420585824e-02, 5.4413218064e-02, -1.3991942256e-02, -7.3511311682e-02, 9.8306147091e-03, 1.0538098831e-01, 2.4767895457e-03, -1.7013983793e-01, -5.3519295197e-02, 3.5729875325e-01, 5.9530013734e-01, 3.5729875325e-01, -5.3519295197e-02, -1.7013983793e-01, 2.4767895457e-03, 1.0538098831e-01, 9.8306147091e-03, -7.3511311682e-02, -1.3991942256e-02, 5.4413218064e-02, 1.5420585824e-02, -4.1549149361e-02, -1.5638192699e-02, 3.2223155290e-02, 1.5213119554e-02, -2.5135038845e-02, -1.4406996028e-02, 1.9583979076e-02, 1.3362938210e-02, -1.5158439259e-02, -1.2171477770e-02, 1.1598799243e-02, 1.0896800128e-02, -8.7303353142e-03, -9.5881685667e-03, 6.4277320980e-03, 8.2841916600e-03, -4.5973156063e-03, -7.0175713933e-03, 3.1633610776e-03, 5.8140101675e-03, -2.0632159584e-03, -4.6937909542e-03, 1.2430372921e-03, 3.6720962046e-03, -6.5548048055e-04, -2.7593013177e-03, 2.5839388583e-04, 1.9613024094e-03, -1.4106495666e-05, -1.2799048805e-03, -1.1093829736e-04, 7.1327754530e-04, 1.4635687092e-04, -2.5647044402e-04, -1.1791553911e-04, -9.8021126546e-05, 4.7605082323e-05, 3.5965967563e-04, 4.6206061884e-05, -5.3942758146e-04, -1.4890118284e-04, 6.4888144112e-04, 2.4899722791e-04, -6.9999979578e-04, -3.3816268708e-04, 7.0454923950e-04, 4.1083915738e-04, -6.7369245331e-04, -4.6388070868e-04, 6.1766717590e-04, 4.9616951008e-04, -5.4554763871e-04, -5.0822117940e-04, 4.6508817914e-04, 5.0179308310e-04, -3.8264756455e-04, -4.7951215941e-04, 3.0318466104e-04, 4.4453252714e-04, -2.3031764274e-04, -4.0023458429e-04, 1.6643173499e-04, 3.4996062912e-04, -1.1285857228e-04, -2.9687173927e-04, 6.9969543240e-05, 2.4371243539e-04, -3.7440682291e-05, -1.9277411182e-04, 1.4403443484e-05, 1.4583183818e-04, 3.7650515294e-07, -1.0413520871e-04, -8.3394585095e-06, 6.8433254890e-05, 1.0994139826e-05, -3.9025740577e-05, -9.8065695691e-06, 1.5831781930e-05, 6.1157778312e-06, 1.5310917825e-06, -1.0766754409e-06, -1.3665196308e-05, -4.3728197481e-06, 2.1313177486e-05, 9.5223982251e-06, -2.5287767236e-05, -1.3887984508e-05, 2.6400053739e-05, 1.7177613167e-05, -2.5425425753e-05, -1.9275907764e-05, 2.3056727953e-05, 2.0203022903e-05, -1.9883422927e-05, -2.0078608383e-05, 1.6380162505e-05, 1.9086646276e-05, -1.2905490830e-05, -1.7443962288e-05, 9.7084647273e-06, 1.5373724961e-05, -6.9412383420e-06, -1.3084991486e-05, 4.6752496998e-06, 1.0758341788e-05, -2.9191987685e-06, -8.5375061091e-06, 1.6368965465e-06, 6.5260611238e-06, -7.6397724595e-07, -4.7889010594e-06, 2.2117927620e-07, 3.3549988889e-06, 7.2763377227e-08, -2.2249377290e-06, -1.9384365527e-07, 1.3774224210e-06, 2.0712149544e-07, -7.7661761489e-07, -1.6394613230e-07, 3.7888894052e-07, 1.0133745579e-07, -1.3853077565e-07, -4.3002365521e-08, 1.2186120186e-08, 1.4084131418e-09, 3.8109090962e-08, 1.9581108834e-08, -4.3206471974e-08"/>
        <PARAMETER NAME="Coefficient_File" VALUE="no_coe_file_loaded"/>
        <PARAMETER NAME="Coefficient_Sets" VALUE="1"/>
        <PARAMETER NAME="Coefficient_Reload" VALUE="false"/>
        <PARAMETER NAME="Filter_Type" VALUE="Decimation"/>
        <PARAMETER NAME="Rate_Change_Type" VALUE="Integer"/>
        <PARAMETER NAME="Interpolation_Rate" VALUE="1"/>
        <PARAMETER NAME="Decimation_Rate" VALUE="2"/>
        <PARAMETER NAME="Zero_Pack_Factor" VALUE="1"/>
        <PARAMETER NAME="Channel_Sequence" VALUE="Basic"/>
        <PARAMETER NAME="Number_Channels" VALUE="1"/>
        <PARAMETER NAME="Select_Pattern" VALUE="All"/>
        <PARAMETER NAME="Pattern_List" VALUE="P4-0,P4-1,P4-2,P4-3,P4-4"/>
        <PARAMETER NAME="Number_Paths" VALUE="4"/>
        <PARAMETER NAME="RateSpecification" VALUE="Frequency_Specification"/>
        <PARAMETER NAME="HardwareOversamplingRate" VALUE="1"/>
        <PARAMETER NAME="SamplePeriod" VALUE="1"/>
        <PARAMETER NAME="Sample_Frequency" VALUE="30.72"/>
        <PARAMETER NAME="Clock_Frequency" VALUE="122.88"/>
        <PARAMETER NAME="Coefficient_Sign" VALUE="Signed"/>
        <PARAMETER NAME="Quantization" VALUE="Quantize_Only"/>
        <PARAMETER NAME="Coefficient_Width" VALUE="24"/>
        <PARAMETER NAME="BestPrecision" VALUE="true"/>
        <PARAMETER NAME="Coefficient_Fractional_Bits" VALUE="23"/>
        <PARAMETER NAME="Coefficient_Structure" VALUE="Inferred"/>
        <PARAMETER NAME="Data_Sign" VALUE="Signed"/>
        <PARAMETER NAME="Data_Width" VALUE="32"/>
        <PARAMETER NAME="Data_Fractional_Bits" VALUE="0"/>
        <PARAMETER NAME="Output_Rounding_Mode" VALUE="Convergent_Rounding_to_Even"/>
        <PARAMETER NAME="Output_Width" VALUE="18"/>
        <PARAMETER NAME="Filter_Architecture" VALUE="Systolic_Multiply_Accumulate"/>
        <PARAMETER NAME="Optimization_Goal" VALUE="Area"/>
        <PARAMETER NAME="Optimization_Selection" VALUE="None"/>
        <PARAMETER NAME="Data_Path_Fanout" VALUE="false"/>
        <PARAMETER NAME="Pre_Adder_Pipeline" VALUE="false"/>
        <PARAMETER NAME="Coefficient_Fanout" VALUE="false"/>
        <PARAMETER NAME="Control_Path_Fanout" VALUE="false"/>
        <PARAMETER NAME="Control_Column_Fanout" VALUE="false"/>
        <PARAMETER NAME="Control_Broadcast_Fanout" VALUE="false"/>
        <PARAMETER NAME="Control_LUT_Pipeline" VALUE="false"/>
        <PARAMETER NAME="No_BRAM_Read_First_Mode" VALUE="false"/>
        <PARAMETER NAME="Optimal_Column_Lengths" VALUE="false"/>
        <PARAMETER NAME="Data_Path_Broadcast" VALUE="false"/>
        <PARAMETER NAME="Disable_Half_Band_Centre_Tap" VALUE="false"/>
        <PARAMETER NAME="No_SRL_Attributes" VALUE="false"/>
        <PARAMETER NAME="Other" VALUE="false"/>
        <PARAMETER NAME="Optimization_List" VALUE="None"/>
        <PARAMETER NAME="Data_Buffer_Type" VALUE="Automatic"/>
        <PARAMETER NAME="Coefficient_Buffer_Type" VALUE="Automatic"/>
        <PARAMETER NAME="Input_Buffer_Type" VALUE="Automatic"/>
        <PARAMETER NAME="Output_Buffer_Type" VALUE="Automatic"/>
        <PARAMETER NAME="Preference_For_Other_Storage" VALUE="Automatic"/>
        <PARAMETER NAME="Multi_Column_Support" VALUE="Automatic"/>
        <PARAMETER NAME="Inter_Column_Pipe_Length" VALUE="4"/>
        <PARAMETER NAME="ColumnConfig" VALUE="18"/>
        <PARAMETER NAME="DATA_Has_TLAST" VALUE="Not_Required"/>
        <PARAMETER NAME="M_DATA_Has_TREADY" VALUE="true"/>
        <PARAMETER NAME="S_DATA_Has_FIFO" VALUE="true"/>
        <PARAMETER NAME="S_DATA_Has_TUSER" VALUE="Not_Required"/>
        <PARAMETER NAME="M_DATA_Has_TUSER" VALUE="Not_Required"/>
        <PARAMETER NAME="DATA_TUSER_Width" VALUE="1"/>
        <PARAMETER NAME="S_CONFIG_Sync_Mode" VALUE="On_Vector"/>
        <PARAMETER NAME="S_CONFIG_Method" VALUE="Single"/>
        <PARAMETER NAME="Num_Reload_Slots" VALUE="1"/>
        <PARAMETER NAME="Has_ACLKEN" VALUE="false"/>
        <PARAMETER NAME="Has_ARESETn" VALUE="true"/>
        <PARAMETER NAME="Reset_Data_Vector" VALUE="true"/>
        <PARAMETER NAME="Blank_Output" VALUE="false"/>
        <PARAMETER NAME="Gen_MIF_from_Spec" VALUE="false"/>
        <PARAMETER NAME="Gen_MIF_from_COE" VALUE="false"/>
        <PARAMETER NAME="Reload_File" VALUE="no_coe_file_loaded"/>
        <PARAMETER NAME="Gen_MIF_Files" VALUE="false"/>
        <PARAMETER NAME="DisplayReloadOrder" VALUE="false"/>
        <PARAMETER NAME="Passband_Min" VALUE="0.0"/>
        <PARAMETER NAME="Passband_Max" VALUE="0.5"/>
        <PARAMETER NAME="Stopband_Min" VALUE="0.5"/>
        <PARAMETER NAME="Stopband_Max" VALUE="1.0"/>
        <PARAMETER NAME="Filter_Selection" VALUE="1"/>
        <PARAMETER NAME="EDK_IPTYPE" VALUE="PERIPHERAL"/>
      </PARAMETERS>
      <PORTS>
        <PORT DIR="I" NAME="aresetn" POLARITY="ACTIVE_LOW" SIGIS="rst" SIGNAME="slice_0_dout">
          <CONNECTIONS>
            <CONNECTION INSTANCE="slice_0" PORT="dout"/>
          </CONNECTIONS>
        </PORT>
        <PORT CLKFREQUENCY="122880000" DIR="I" NAME="aclk" SIGIS="clk" SIGNAME="pll_0_clk_out1">
          <CONNECTIONS>
            <CONNECTION INSTANCE="pll_0" PORT="clk_out1"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" NAME="s_axis_data_tvalid" SIGIS="undef" SIGNAME="comb_0_m_axis_tvalid">
          <CONNECTIONS>
            <CONNECTION INSTANCE="comb_0" PORT="m_axis_tvalid"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" NAME="s_axis_data_tready" SIGIS="undef" SIGNAME="comb_0_m_axis_tready">
          <CONNECTIONS>
            <CONNECTION INSTANCE="comb_0" PORT="m_axis_tready"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" LEFT="127" NAME="s_axis_data_tdata" RIGHT="0" SIGIS="undef" SIGNAME="comb_0_m_axis_tdata">
          <CONNECTIONS>
            <CONNECTION INSTANCE="comb_0" PORT="m_axis_tdata"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" NAME="m_axis_data_tvalid" SIGIS="undef" SIGNAME="fir_0_m_axis_data_tvalid">
          <CONNECTIONS>
            <CONNECTION INSTANCE="subset_0" PORT="s_axis_tvalid"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" NAME="m_axis_data_tready" SIGIS="undef" SIGNAME="fir_0_m_axis_data_tready">
          <CONNECTIONS>
            <CONNECTION INSTANCE="subset_0" PORT="s_axis_tready"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" LEFT="95" NAME="m_axis_data_tdata" RIGHT="0" SIGIS="undef" SIGNAME="fir_0_m_axis_data_tdata">
          <CONNECTIONS>
            <CONNECTION INSTANCE="subset_0" PORT="s_axis_tdata"/>
          </CONNECTIONS>
        </PORT>
      </PORTS>
      <BUSINTERFACES>
        <BUSINTERFACE BUSNAME="comb_0_M_AXIS" NAME="S_AXIS_DATA" TYPE="SLAVE" VLNV="xilinx.com:interface:axis:1.0">
          <PARAMETER NAME="TDATA_NUM_BYTES" VALUE="16"/>
          <PARAMETER NAME="TDEST_WIDTH" VALUE="0"/>
          <PARAMETER NAME="TID_WIDTH" VALUE="0"/>
          <PARAMETER NAME="TUSER_WIDTH" VALUE="0"/>
          <PARAMETER NAME="HAS_TREADY" VALUE="1"/>
          <PARAMETER NAME="HAS_TSTRB" VALUE="0"/>
          <PARAMETER NAME="HAS_TKEEP" VALUE="0"/>
          <PARAMETER NAME="HAS_TLAST" VALUE="0"/>
          <PARAMETER NAME="FREQ_HZ" VALUE="122880000"/>
          <PARAMETER NAME="PHASE" VALUE="0.0"/>
          <PARAMETER NAME="CLK_DOMAIN" VALUE="system_pll_0_0_clk_out1"/>
          <PARAMETER NAME="LAYERED_METADATA" VALUE="undef"/>
          <PARAMETER NAME="INSERT_VIP" VALUE="0"/>
          <PORTMAPS>
            <PORTMAP LOGICAL="TDATA" PHYSICAL="s_axis_data_tdata"/>
            <PORTMAP LOGICAL="TREADY" PHYSICAL="s_axis_data_tready"/>
            <PORTMAP LOGICAL="TVALID" PHYSICAL="s_axis_data_tvalid"/>
          </PORTMAPS>
        </BUSINTERFACE>
        <BUSINTERFACE BUSNAME="fir_0_M_AXIS_DATA" NAME="M_AXIS_DATA" TYPE="INITIATOR" VLNV="xilinx.com:interface:axis:1.0">
          <PARAMETER NAME="TDATA_NUM_BYTES" VALUE="12"/>
          <PARAMETER NAME="TDEST_WIDTH" VALUE="0"/>
          <PARAMETER NAME="TID_WIDTH" VALUE="0"/>
          <PARAMETER NAME="TUSER_WIDTH" VALUE="0"/>
          <PARAMETER NAME="HAS_TREADY" VALUE="1"/>
          <PARAMETER NAME="HAS_TSTRB" VALUE="0"/>
          <PARAMETER NAME="HAS_TKEEP" VALUE="0"/>
          <PARAMETER NAME="HAS_TLAST" VALUE="0"/>
          <PARAMETER NAME="FREQ_HZ" VALUE="122880000"/>
          <PARAMETER NAME="PHASE" VALUE="0.0"/>
          <PARAMETER NAME="CLK_DOMAIN" VALUE="system_pll_0_0_clk_out1"/>
          <PARAMETER NAME="LAYERED_METADATA" VALUE="xilinx.com:interface:datatypes:1.0 {TDATA {datatype {name {attribs {resolve_type immediate dependency {} format string minimum {} maximum {}} value {}} bitwidth {attribs {resolve_type automatic dependency {} format long minimum {} maximum {}} value 90} bitoffset {attribs {resolve_type immediate dependency {} format long minimum {} maximum {}} value 0} array_type {name {attribs {resolve_type immediate dependency {} format string minimum {} maximum {}} value chan} size {attribs {resolve_type generated dependency chan_size format long minimum {} maximum {}} value 1} stride {attribs {resolve_type generated dependency chan_stride format long minimum {} maximum {}} value 96} datatype {name {attribs {resolve_type immediate dependency {} format string minimum {} maximum {}} value {}} bitwidth {attribs {resolve_type automatic dependency {} format long minimum {} maximum {}} value 90} bitoffset {attribs {resolve_type immediate dependency {} format long minimum {} maximum {}} value 0} array_type {name {attribs {resolve_type immediate dependency {} format string minimum {} maximum {}} value path} size {attribs {resolve_type generated dependency path_size format long minimum {} maximum {}} value 4} stride {attribs {resolve_type generated dependency path_stride format long minimum {} maximum {}} value 24} datatype {name {attribs {resolve_type immediate dependency {} format string minimum {} maximum {}} value {}} bitwidth {attribs {resolve_type generated dependency out_width format long minimum {} maximum {}} value 18} bitoffset {attribs {resolve_type immediate dependency {} format long minimum {} maximum {}} value 0} real {fixed {fractwidth {attribs {resolve_type generated dependency out_fractwidth format long minimum {} maximum {}} value 0} signed {attribs {resolve_type generated dependency out_signed format bool minimum {} maximum {}} value true}}}}}}}}} TDATA_WIDTH 96 TUSER {datatype {name {attribs {resolve_type immediate dependency {} format string minimum {} maximum {}} value {}} bitwidth {attribs {resolve_type automatic dependency {} format long minimum {} maximum {}} value 0} bitoffset {attribs {resolve_type immediate dependency {} format long minimum {} maximum {}} value 0} struct {field_data_valid {name {attribs {resolve_type immediate dependency {} format string minimum {} maximum {}} value data_valid} enabled {attribs {resolve_type generated dependency data_valid_enabled format bool minimum {} maximum {}} value false} datatype {name {attribs {resolve_type immediate dependency {} format string minimum {} maximum {}} value {}} bitwidth {attribs {resolve_type generated dependency data_valid_bitwidth format long minimum {} maximum {}} value 0} bitoffset {attribs {resolve_type immediate dependency {} format long minimum {} maximum {}} value 0}}} field_chanid {name {attribs {resolve_type immediate dependency {} format string minimum {} maximum {}} value chanid} enabled {attribs {resolve_type generated dependency chanid_enabled format bool minimum {} maximum {}} value false} datatype {name {attribs {resolve_type immediate dependency {} format string minimum {} maximum {}} value {}} bitwidth {attribs {resolve_type generated dependency chanid_bitwidth format long minimum {} maximum {}} value 0} bitoffset {attribs {resolve_type generated dependency chanid_bitoffset format long minimum {} maximum {}} value 0} integer {signed {attribs {resolve_type immediate dependency {} format bool minimum {} maximum {}} value false}}}} field_user {name {attribs {resolve_type immediate dependency {} format string minimum {} maximum {}} value user} enabled {attribs {resolve_type generated dependency user_enabled format bool minimum {} maximum {}} value false} datatype {name {attribs {resolve_type immediate dependency {} format string minimum {} maximum {}} value {}} bitwidth {attribs {resolve_type generated dependency user_bitwidth format long minimum {} maximum {}} value 0} bitoffset {attribs {resolve_type generated dependency user_bitoffset format long minimum {} maximum {}} value 0}}}}}} TUSER_WIDTH 0}"/>
          <PARAMETER NAME="INSERT_VIP" VALUE="0"/>
          <PORTMAPS>
            <PORTMAP LOGICAL="TDATA" PHYSICAL="m_axis_data_tdata"/>
            <PORTMAP LOGICAL="TREADY" PHYSICAL="m_axis_data_tready"/>
            <PORTMAP LOGICAL="TVALID" PHYSICAL="m_axis_data_tvalid"/>
          </PORTMAPS>
        </BUSINTERFACE>
      </BUSINTERFACES>
    </MODULE>
    <MODULE COREREVISION="1" FULLNAME="/fsk_detector_1_00_0" HWVERSION="1.0" INSTANCE="fsk_detector_1_00_0" IPTYPE="PERIPHERAL" IS_ENABLE="1" MODCLASS="PERIPHERAL" MODTYPE="fsk_detector_1_00" VLNV="pavel-demin:user:fsk_detector_1_00:1.0">
      <DOCUMENTS/>
      <PARAMETERS>
        <PARAMETER NAME="DATA_WIDTH" VALUE="32"/>
        <PARAMETER NAME="Component_Name" VALUE="system_fsk_detector_1_00_0_0"/>
        <PARAMETER NAME="EDK_IPTYPE" VALUE="PERIPHERAL"/>
      </PARAMETERS>
      <PORTS>
        <PORT CLKFREQUENCY="122880000" DIR="I" NAME="aclk" SIGIS="clk" SIGNAME="pll_0_clk_out1">
          <CONNECTIONS>
            <CONNECTION INSTANCE="pll_0" PORT="clk_out1"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" NAME="aresetn" POLARITY="ACTIVE_LOW" SIGIS="rst" SIGNAME="slice_1_dout">
          <CONNECTIONS>
            <CONNECTION INSTANCE="slice_1" PORT="dout"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" LEFT="31" NAME="in_data" RIGHT="0" SIGIS="undef"/>
        <PORT DIR="I" NAME="in_valid" SIGIS="undef"/>
        <PORT DIR="O" NAME="in_ready" SIGIS="undef"/>
        <PORT DIR="O" LEFT="31" NAME="out_data" RIGHT="0" SIGIS="undef" SIGNAME="fsk_detector_1_00_0_out_data">
          <CONNECTIONS>
            <CONNECTION INSTANCE="slice_GPIO_out1" PORT="din"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" NAME="out_valid" SIGIS="undef"/>
        <PORT DIR="I" NAME="out_ready" SIGIS="undef" SIGNAME="const_GPIO_out1_dout">
          <CONNECTIONS>
            <CONNECTION INSTANCE="const_GPIO_out1" PORT="dout"/>
          </CONNECTIONS>
        </PORT>
      </PORTS>
      <BUSINTERFACES/>
    </MODULE>
    <MODULE COREREVISION="1" FULLNAME="/hub_0" HWVERSION="1.0" INSTANCE="hub_0" IPTYPE="PERIPHERAL" IS_ENABLE="1" MODCLASS="PERIPHERAL" MODTYPE="axi_hub" VLNV="pavel-demin:user:axi_hub:1.0">
      <DOCUMENTS/>
      <PARAMETERS>
        <PARAMETER NAME="CFG_DATA_WIDTH" VALUE="224"/>
        <PARAMETER NAME="STS_DATA_WIDTH" VALUE="32"/>
        <PARAMETER NAME="Component_Name" VALUE="system_hub_0_0"/>
        <PARAMETER NAME="EDK_IPTYPE" VALUE="PERIPHERAL"/>
      </PARAMETERS>
      <PORTS>
        <PORT CLKFREQUENCY="122880000" DIR="I" NAME="aclk" SIGIS="clk" SIGNAME="pll_0_clk_out1">
          <CONNECTIONS>
            <CONNECTION INSTANCE="pll_0" PORT="clk_out1"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" NAME="aresetn" POLARITY="ACTIVE_LOW" SIGIS="rst" SIGNAME="rst_0_peripheral_aresetn">
          <CONNECTIONS>
            <CONNECTION INSTANCE="rst_0" PORT="peripheral_aresetn"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" LEFT="11" NAME="s_axi_awid" RIGHT="0" SIGIS="undef" SIGNAME="hub_0_s_axi_awid">
          <CONNECTIONS>
            <CONNECTION INSTANCE="ps_0" PORT="M_AXI_GP0_AWID"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" LEFT="31" NAME="s_axi_awaddr" RIGHT="0" SIGIS="undef" SIGNAME="hub_0_s_axi_awaddr">
          <CONNECTIONS>
            <CONNECTION INSTANCE="ps_0" PORT="M_AXI_GP0_AWADDR"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" NAME="s_axi_awvalid" SIGIS="undef" SIGNAME="hub_0_s_axi_awvalid">
          <CONNECTIONS>
            <CONNECTION INSTANCE="ps_0" PORT="M_AXI_GP0_AWVALID"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" NAME="s_axi_awready" SIGIS="undef" SIGNAME="hub_0_s_axi_awready">
          <CONNECTIONS>
            <CONNECTION INSTANCE="ps_0" PORT="M_AXI_GP0_AWREADY"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" LEFT="3" NAME="s_axi_wstrb" RIGHT="0" SIGIS="undef" SIGNAME="hub_0_s_axi_wstrb">
          <CONNECTIONS>
            <CONNECTION INSTANCE="ps_0" PORT="M_AXI_GP0_WSTRB"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" NAME="s_axi_wlast" SIGIS="undef" SIGNAME="hub_0_s_axi_wlast">
          <CONNECTIONS>
            <CONNECTION INSTANCE="ps_0" PORT="M_AXI_GP0_WLAST"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" LEFT="31" NAME="s_axi_wdata" RIGHT="0" SIGIS="undef" SIGNAME="hub_0_s_axi_wdata">
          <CONNECTIONS>
            <CONNECTION INSTANCE="ps_0" PORT="M_AXI_GP0_WDATA"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" NAME="s_axi_wvalid" SIGIS="undef" SIGNAME="hub_0_s_axi_wvalid">
          <CONNECTIONS>
            <CONNECTION INSTANCE="ps_0" PORT="M_AXI_GP0_WVALID"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" NAME="s_axi_wready" SIGIS="undef" SIGNAME="hub_0_s_axi_wready">
          <CONNECTIONS>
            <CONNECTION INSTANCE="ps_0" PORT="M_AXI_GP0_WREADY"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" LEFT="11" NAME="s_axi_bid" RIGHT="0" SIGIS="undef" SIGNAME="hub_0_s_axi_bid">
          <CONNECTIONS>
            <CONNECTION INSTANCE="ps_0" PORT="M_AXI_GP0_BID"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" NAME="s_axi_bvalid" SIGIS="undef" SIGNAME="hub_0_s_axi_bvalid">
          <CONNECTIONS>
            <CONNECTION INSTANCE="ps_0" PORT="M_AXI_GP0_BVALID"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" NAME="s_axi_bready" SIGIS="undef" SIGNAME="hub_0_s_axi_bready">
          <CONNECTIONS>
            <CONNECTION INSTANCE="ps_0" PORT="M_AXI_GP0_BREADY"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" LEFT="11" NAME="s_axi_arid" RIGHT="0" SIGIS="undef" SIGNAME="hub_0_s_axi_arid">
          <CONNECTIONS>
            <CONNECTION INSTANCE="ps_0" PORT="M_AXI_GP0_ARID"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" LEFT="3" NAME="s_axi_arlen" RIGHT="0" SIGIS="undef" SIGNAME="hub_0_s_axi_arlen">
          <CONNECTIONS>
            <CONNECTION INSTANCE="ps_0" PORT="M_AXI_GP0_ARLEN"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" LEFT="31" NAME="s_axi_araddr" RIGHT="0" SIGIS="undef" SIGNAME="hub_0_s_axi_araddr">
          <CONNECTIONS>
            <CONNECTION INSTANCE="ps_0" PORT="M_AXI_GP0_ARADDR"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" NAME="s_axi_arvalid" SIGIS="undef" SIGNAME="hub_0_s_axi_arvalid">
          <CONNECTIONS>
            <CONNECTION INSTANCE="ps_0" PORT="M_AXI_GP0_ARVALID"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" NAME="s_axi_arready" SIGIS="undef" SIGNAME="hub_0_s_axi_arready">
          <CONNECTIONS>
            <CONNECTION INSTANCE="ps_0" PORT="M_AXI_GP0_ARREADY"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" LEFT="11" NAME="s_axi_rid" RIGHT="0" SIGIS="undef" SIGNAME="hub_0_s_axi_rid">
          <CONNECTIONS>
            <CONNECTION INSTANCE="ps_0" PORT="M_AXI_GP0_RID"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" NAME="s_axi_rlast" SIGIS="undef" SIGNAME="hub_0_s_axi_rlast">
          <CONNECTIONS>
            <CONNECTION INSTANCE="ps_0" PORT="M_AXI_GP0_RLAST"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" LEFT="31" NAME="s_axi_rdata" RIGHT="0" SIGIS="undef" SIGNAME="hub_0_s_axi_rdata">
          <CONNECTIONS>
            <CONNECTION INSTANCE="ps_0" PORT="M_AXI_GP0_RDATA"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" NAME="s_axi_rvalid" SIGIS="undef" SIGNAME="hub_0_s_axi_rvalid">
          <CONNECTIONS>
            <CONNECTION INSTANCE="ps_0" PORT="M_AXI_GP0_RVALID"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" NAME="s_axi_rready" SIGIS="undef" SIGNAME="hub_0_s_axi_rready">
          <CONNECTIONS>
            <CONNECTION INSTANCE="ps_0" PORT="M_AXI_GP0_RREADY"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" LEFT="223" NAME="cfg_data" RIGHT="0" SIGIS="undef" SIGNAME="hub_0_cfg_data">
          <CONNECTIONS>
            <CONNECTION INSTANCE="slice_0" PORT="din"/>
            <CONNECTION INSTANCE="slice_1" PORT="din"/>
            <CONNECTION INSTANCE="slice_2" PORT="din"/>
            <CONNECTION INSTANCE="slice_3" PORT="din"/>
            <CONNECTION INSTANCE="slice_4" PORT="din"/>
            <CONNECTION INSTANCE="slice_5" PORT="din"/>
            <CONNECTION INSTANCE="slice_6" PORT="din"/>
            <CONNECTION INSTANCE="slice_7" PORT="din"/>
            <CONNECTION INSTANCE="slice_GPIO_out" PORT="din"/>
            <CONNECTION INSTANCE="slice_8" PORT="din"/>
            <CONNECTION INSTANCE="slice_9" PORT="din"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" LEFT="31" NAME="sts_data" RIGHT="0" SIGIS="undef" SIGNAME="writer_0_sts_data">
          <CONNECTIONS>
            <CONNECTION INSTANCE="writer_0" PORT="sts_data"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" NAME="b00_bram_clk" SIGIS="clk"/>
        <PORT DIR="O" NAME="b00_bram_rst" SIGIS="rst"/>
        <PORT DIR="O" NAME="b00_bram_en" SIGIS="undef"/>
        <PORT DIR="O" LEFT="3" NAME="b00_bram_we" RIGHT="0" SIGIS="undef"/>
        <PORT DIR="O" LEFT="21" NAME="b00_bram_addr" RIGHT="0" SIGIS="undef"/>
        <PORT DIR="O" LEFT="31" NAME="b00_bram_wdata" RIGHT="0" SIGIS="undef"/>
        <PORT DIR="I" LEFT="31" NAME="b00_bram_rdata" RIGHT="0" SIGIS="undef"/>
        <PORT DIR="I" LEFT="31" NAME="s00_axis_tdata" RIGHT="0" SIGIS="undef"/>
        <PORT DIR="I" NAME="s00_axis_tvalid" SIGIS="undef"/>
        <PORT DIR="O" NAME="s00_axis_tready" SIGIS="undef"/>
        <PORT DIR="O" LEFT="31" NAME="m00_axis_tdata" RIGHT="0" SIGIS="undef"/>
        <PORT DIR="O" NAME="m00_axis_tvalid" SIGIS="undef"/>
        <PORT DIR="I" NAME="m00_axis_tready" SIGIS="undef"/>
        <PORT DIR="O" NAME="b01_bram_clk" SIGIS="clk"/>
        <PORT DIR="O" NAME="b01_bram_rst" SIGIS="rst"/>
        <PORT DIR="O" NAME="b01_bram_en" SIGIS="undef"/>
        <PORT DIR="O" LEFT="3" NAME="b01_bram_we" RIGHT="0" SIGIS="undef"/>
        <PORT DIR="O" LEFT="21" NAME="b01_bram_addr" RIGHT="0" SIGIS="undef"/>
        <PORT DIR="O" LEFT="31" NAME="b01_bram_wdata" RIGHT="0" SIGIS="undef"/>
        <PORT DIR="I" LEFT="31" NAME="b01_bram_rdata" RIGHT="0" SIGIS="undef"/>
        <PORT DIR="I" LEFT="31" NAME="s01_axis_tdata" RIGHT="0" SIGIS="undef"/>
        <PORT DIR="I" NAME="s01_axis_tvalid" SIGIS="undef"/>
        <PORT DIR="O" NAME="s01_axis_tready" SIGIS="undef"/>
        <PORT DIR="O" LEFT="31" NAME="m01_axis_tdata" RIGHT="0" SIGIS="undef"/>
        <PORT DIR="O" NAME="m01_axis_tvalid" SIGIS="undef"/>
        <PORT DIR="I" NAME="m01_axis_tready" SIGIS="undef"/>
        <PORT DIR="O" NAME="b02_bram_clk" SIGIS="clk"/>
        <PORT DIR="O" NAME="b02_bram_rst" SIGIS="rst"/>
        <PORT DIR="O" NAME="b02_bram_en" SIGIS="undef"/>
        <PORT DIR="O" LEFT="3" NAME="b02_bram_we" RIGHT="0" SIGIS="undef"/>
        <PORT DIR="O" LEFT="21" NAME="b02_bram_addr" RIGHT="0" SIGIS="undef"/>
        <PORT DIR="O" LEFT="31" NAME="b02_bram_wdata" RIGHT="0" SIGIS="undef"/>
        <PORT DIR="I" LEFT="31" NAME="b02_bram_rdata" RIGHT="0" SIGIS="undef"/>
        <PORT DIR="I" LEFT="31" NAME="s02_axis_tdata" RIGHT="0" SIGIS="undef"/>
        <PORT DIR="I" NAME="s02_axis_tvalid" SIGIS="undef"/>
        <PORT DIR="O" NAME="s02_axis_tready" SIGIS="undef"/>
        <PORT DIR="O" LEFT="31" NAME="m02_axis_tdata" RIGHT="0" SIGIS="undef"/>
        <PORT DIR="O" NAME="m02_axis_tvalid" SIGIS="undef"/>
        <PORT DIR="I" NAME="m02_axis_tready" SIGIS="undef"/>
        <PORT DIR="O" NAME="b03_bram_clk" SIGIS="clk"/>
        <PORT DIR="O" NAME="b03_bram_rst" SIGIS="rst"/>
        <PORT DIR="O" NAME="b03_bram_en" SIGIS="undef"/>
        <PORT DIR="O" LEFT="3" NAME="b03_bram_we" RIGHT="0" SIGIS="undef"/>
        <PORT DIR="O" LEFT="21" NAME="b03_bram_addr" RIGHT="0" SIGIS="undef"/>
        <PORT DIR="O" LEFT="31" NAME="b03_bram_wdata" RIGHT="0" SIGIS="undef"/>
        <PORT DIR="I" LEFT="31" NAME="b03_bram_rdata" RIGHT="0" SIGIS="undef"/>
        <PORT DIR="I" LEFT="31" NAME="s03_axis_tdata" RIGHT="0" SIGIS="undef"/>
        <PORT DIR="I" NAME="s03_axis_tvalid" SIGIS="undef"/>
        <PORT DIR="O" NAME="s03_axis_tready" SIGIS="undef"/>
        <PORT DIR="O" LEFT="31" NAME="m03_axis_tdata" RIGHT="0" SIGIS="undef"/>
        <PORT DIR="O" NAME="m03_axis_tvalid" SIGIS="undef"/>
        <PORT DIR="I" NAME="m03_axis_tready" SIGIS="undef"/>
        <PORT DIR="O" NAME="b04_bram_clk" SIGIS="clk"/>
        <PORT DIR="O" NAME="b04_bram_rst" SIGIS="rst"/>
        <PORT DIR="O" NAME="b04_bram_en" SIGIS="undef"/>
        <PORT DIR="O" LEFT="3" NAME="b04_bram_we" RIGHT="0" SIGIS="undef"/>
        <PORT DIR="O" LEFT="21" NAME="b04_bram_addr" RIGHT="0" SIGIS="undef"/>
        <PORT DIR="O" LEFT="31" NAME="b04_bram_wdata" RIGHT="0" SIGIS="undef"/>
        <PORT DIR="I" LEFT="31" NAME="b04_bram_rdata" RIGHT="0" SIGIS="undef"/>
        <PORT DIR="I" LEFT="31" NAME="s04_axis_tdata" RIGHT="0" SIGIS="undef"/>
        <PORT DIR="I" NAME="s04_axis_tvalid" SIGIS="undef"/>
        <PORT DIR="O" NAME="s04_axis_tready" SIGIS="undef"/>
        <PORT DIR="O" LEFT="31" NAME="m04_axis_tdata" RIGHT="0" SIGIS="undef"/>
        <PORT DIR="O" NAME="m04_axis_tvalid" SIGIS="undef"/>
        <PORT DIR="I" NAME="m04_axis_tready" SIGIS="undef"/>
        <PORT DIR="O" NAME="b05_bram_clk" SIGIS="clk"/>
        <PORT DIR="O" NAME="b05_bram_rst" SIGIS="rst"/>
        <PORT DIR="O" NAME="b05_bram_en" SIGIS="undef"/>
        <PORT DIR="O" LEFT="3" NAME="b05_bram_we" RIGHT="0" SIGIS="undef"/>
        <PORT DIR="O" LEFT="21" NAME="b05_bram_addr" RIGHT="0" SIGIS="undef"/>
        <PORT DIR="O" LEFT="31" NAME="b05_bram_wdata" RIGHT="0" SIGIS="undef"/>
        <PORT DIR="I" LEFT="31" NAME="b05_bram_rdata" RIGHT="0" SIGIS="undef"/>
        <PORT DIR="I" LEFT="31" NAME="s05_axis_tdata" RIGHT="0" SIGIS="undef"/>
        <PORT DIR="I" NAME="s05_axis_tvalid" SIGIS="undef"/>
        <PORT DIR="O" NAME="s05_axis_tready" SIGIS="undef"/>
        <PORT DIR="O" LEFT="31" NAME="m05_axis_tdata" RIGHT="0" SIGIS="undef"/>
        <PORT DIR="O" NAME="m05_axis_tvalid" SIGIS="undef"/>
        <PORT DIR="I" NAME="m05_axis_tready" SIGIS="undef"/>
      </PORTS>
      <BUSINTERFACES>
        <BUSINTERFACE BUSNAME="__NOC__" NAME="b00_bram" TYPE="INITIATOR" VLNV="xilinx.com:interface:bram:1.0">
          <PARAMETER NAME="MEM_SIZE" VALUE="8192"/>
          <PARAMETER NAME="MEM_WIDTH" VALUE="32"/>
          <PARAMETER NAME="MEM_ECC" VALUE="NONE"/>
          <PARAMETER NAME="MASTER_TYPE" VALUE="OTHER"/>
          <PARAMETER NAME="READ_WRITE_MODE"/>
          <PARAMETER NAME="READ_LATENCY" VALUE="1"/>
          <PORTMAPS>
            <PORTMAP LOGICAL="EN" PHYSICAL="b00_bram_en"/>
            <PORTMAP LOGICAL="DOUT" PHYSICAL="b00_bram_rdata"/>
            <PORTMAP LOGICAL="DIN" PHYSICAL="b00_bram_wdata"/>
            <PORTMAP LOGICAL="WE" PHYSICAL="b00_bram_we"/>
            <PORTMAP LOGICAL="ADDR" PHYSICAL="b00_bram_addr"/>
            <PORTMAP LOGICAL="CLK" PHYSICAL="b00_bram_clk"/>
            <PORTMAP LOGICAL="RST" PHYSICAL="b00_bram_rst"/>
          </PORTMAPS>
        </BUSINTERFACE>
        <BUSINTERFACE BUSNAME="__NOC__" NAME="b01_bram" TYPE="INITIATOR" VLNV="xilinx.com:interface:bram:1.0">
          <PARAMETER NAME="MEM_SIZE" VALUE="8192"/>
          <PARAMETER NAME="MEM_WIDTH" VALUE="32"/>
          <PARAMETER NAME="MEM_ECC" VALUE="NONE"/>
          <PARAMETER NAME="MASTER_TYPE" VALUE="OTHER"/>
          <PARAMETER NAME="READ_WRITE_MODE"/>
          <PARAMETER NAME="READ_LATENCY" VALUE="1"/>
          <PORTMAPS>
            <PORTMAP LOGICAL="EN" PHYSICAL="b01_bram_en"/>
            <PORTMAP LOGICAL="DOUT" PHYSICAL="b01_bram_rdata"/>
            <PORTMAP LOGICAL="DIN" PHYSICAL="b01_bram_wdata"/>
            <PORTMAP LOGICAL="WE" PHYSICAL="b01_bram_we"/>
            <PORTMAP LOGICAL="ADDR" PHYSICAL="b01_bram_addr"/>
            <PORTMAP LOGICAL="CLK" PHYSICAL="b01_bram_clk"/>
            <PORTMAP LOGICAL="RST" PHYSICAL="b01_bram_rst"/>
          </PORTMAPS>
        </BUSINTERFACE>
        <BUSINTERFACE BUSNAME="__NOC__" NAME="b02_bram" TYPE="INITIATOR" VLNV="xilinx.com:interface:bram:1.0">
          <PARAMETER NAME="MEM_SIZE" VALUE="8192"/>
          <PARAMETER NAME="MEM_WIDTH" VALUE="32"/>
          <PARAMETER NAME="MEM_ECC" VALUE="NONE"/>
          <PARAMETER NAME="MASTER_TYPE" VALUE="OTHER"/>
          <PARAMETER NAME="READ_WRITE_MODE"/>
          <PARAMETER NAME="READ_LATENCY" VALUE="1"/>
          <PORTMAPS>
            <PORTMAP LOGICAL="EN" PHYSICAL="b02_bram_en"/>
            <PORTMAP LOGICAL="DOUT" PHYSICAL="b02_bram_rdata"/>
            <PORTMAP LOGICAL="DIN" PHYSICAL="b02_bram_wdata"/>
            <PORTMAP LOGICAL="WE" PHYSICAL="b02_bram_we"/>
            <PORTMAP LOGICAL="ADDR" PHYSICAL="b02_bram_addr"/>
            <PORTMAP LOGICAL="CLK" PHYSICAL="b02_bram_clk"/>
            <PORTMAP LOGICAL="RST" PHYSICAL="b02_bram_rst"/>
          </PORTMAPS>
        </BUSINTERFACE>
        <BUSINTERFACE BUSNAME="__NOC__" NAME="b03_bram" TYPE="INITIATOR" VLNV="xilinx.com:interface:bram:1.0">
          <PARAMETER NAME="MEM_SIZE" VALUE="8192"/>
          <PARAMETER NAME="MEM_WIDTH" VALUE="32"/>
          <PARAMETER NAME="MEM_ECC" VALUE="NONE"/>
          <PARAMETER NAME="MASTER_TYPE" VALUE="OTHER"/>
          <PARAMETER NAME="READ_WRITE_MODE"/>
          <PARAMETER NAME="READ_LATENCY" VALUE="1"/>
          <PORTMAPS>
            <PORTMAP LOGICAL="EN" PHYSICAL="b03_bram_en"/>
            <PORTMAP LOGICAL="DOUT" PHYSICAL="b03_bram_rdata"/>
            <PORTMAP LOGICAL="DIN" PHYSICAL="b03_bram_wdata"/>
            <PORTMAP LOGICAL="WE" PHYSICAL="b03_bram_we"/>
            <PORTMAP LOGICAL="ADDR" PHYSICAL="b03_bram_addr"/>
            <PORTMAP LOGICAL="CLK" PHYSICAL="b03_bram_clk"/>
            <PORTMAP LOGICAL="RST" PHYSICAL="b03_bram_rst"/>
          </PORTMAPS>
        </BUSINTERFACE>
        <BUSINTERFACE BUSNAME="__NOC__" NAME="b04_bram" TYPE="INITIATOR" VLNV="xilinx.com:interface:bram:1.0">
          <PARAMETER NAME="MEM_SIZE" VALUE="8192"/>
          <PARAMETER NAME="MEM_WIDTH" VALUE="32"/>
          <PARAMETER NAME="MEM_ECC" VALUE="NONE"/>
          <PARAMETER NAME="MASTER_TYPE" VALUE="OTHER"/>
          <PARAMETER NAME="READ_WRITE_MODE"/>
          <PARAMETER NAME="READ_LATENCY" VALUE="1"/>
          <PORTMAPS>
            <PORTMAP LOGICAL="EN" PHYSICAL="b04_bram_en"/>
            <PORTMAP LOGICAL="DOUT" PHYSICAL="b04_bram_rdata"/>
            <PORTMAP LOGICAL="DIN" PHYSICAL="b04_bram_wdata"/>
            <PORTMAP LOGICAL="WE" PHYSICAL="b04_bram_we"/>
            <PORTMAP LOGICAL="ADDR" PHYSICAL="b04_bram_addr"/>
            <PORTMAP LOGICAL="CLK" PHYSICAL="b04_bram_clk"/>
            <PORTMAP LOGICAL="RST" PHYSICAL="b04_bram_rst"/>
          </PORTMAPS>
        </BUSINTERFACE>
        <BUSINTERFACE BUSNAME="__NOC__" NAME="b05_bram" TYPE="INITIATOR" VLNV="xilinx.com:interface:bram:1.0">
          <PARAMETER NAME="MEM_SIZE" VALUE="8192"/>
          <PARAMETER NAME="MEM_WIDTH" VALUE="32"/>
          <PARAMETER NAME="MEM_ECC" VALUE="NONE"/>
          <PARAMETER NAME="MASTER_TYPE" VALUE="OTHER"/>
          <PARAMETER NAME="READ_WRITE_MODE"/>
          <PARAMETER NAME="READ_LATENCY" VALUE="1"/>
          <PORTMAPS>
            <PORTMAP LOGICAL="EN" PHYSICAL="b05_bram_en"/>
            <PORTMAP LOGICAL="DOUT" PHYSICAL="b05_bram_rdata"/>
            <PORTMAP LOGICAL="DIN" PHYSICAL="b05_bram_wdata"/>
            <PORTMAP LOGICAL="WE" PHYSICAL="b05_bram_we"/>
            <PORTMAP LOGICAL="ADDR" PHYSICAL="b05_bram_addr"/>
            <PORTMAP LOGICAL="CLK" PHYSICAL="b05_bram_clk"/>
            <PORTMAP LOGICAL="RST" PHYSICAL="b05_bram_rst"/>
          </PORTMAPS>
        </BUSINTERFACE>
        <BUSINTERFACE BUSNAME="__NOC__" NAME="m00_axis" TYPE="INITIATOR" VLNV="xilinx.com:interface:axis:1.0">
          <PARAMETER NAME="TDATA_NUM_BYTES" VALUE="4"/>
          <PARAMETER NAME="TDEST_WIDTH" VALUE="0"/>
          <PARAMETER NAME="TID_WIDTH" VALUE="0"/>
          <PARAMETER NAME="TUSER_WIDTH" VALUE="0"/>
          <PARAMETER NAME="HAS_TREADY" VALUE="1"/>
          <PARAMETER NAME="HAS_TSTRB" VALUE="0"/>
          <PARAMETER NAME="HAS_TKEEP" VALUE="0"/>
          <PARAMETER NAME="HAS_TLAST" VALUE="0"/>
          <PARAMETER NAME="FREQ_HZ" VALUE="122880000"/>
          <PARAMETER NAME="PHASE" VALUE="0.0"/>
          <PARAMETER NAME="CLK_DOMAIN" VALUE="system_pll_0_0_clk_out1"/>
          <PARAMETER NAME="LAYERED_METADATA" VALUE="undef"/>
          <PARAMETER NAME="INSERT_VIP" VALUE="0"/>
          <PORTMAPS>
            <PORTMAP LOGICAL="TDATA" PHYSICAL="m00_axis_tdata"/>
            <PORTMAP LOGICAL="TVALID" PHYSICAL="m00_axis_tvalid"/>
            <PORTMAP LOGICAL="TREADY" PHYSICAL="m00_axis_tready"/>
          </PORTMAPS>
        </BUSINTERFACE>
        <BUSINTERFACE BUSNAME="__NOC__" NAME="m01_axis" TYPE="INITIATOR" VLNV="xilinx.com:interface:axis:1.0">
          <PARAMETER NAME="TDATA_NUM_BYTES" VALUE="4"/>
          <PARAMETER NAME="TDEST_WIDTH" VALUE="0"/>
          <PARAMETER NAME="TID_WIDTH" VALUE="0"/>
          <PARAMETER NAME="TUSER_WIDTH" VALUE="0"/>
          <PARAMETER NAME="HAS_TREADY" VALUE="1"/>
          <PARAMETER NAME="HAS_TSTRB" VALUE="0"/>
          <PARAMETER NAME="HAS_TKEEP" VALUE="0"/>
          <PARAMETER NAME="HAS_TLAST" VALUE="0"/>
          <PARAMETER NAME="FREQ_HZ" VALUE="122880000"/>
          <PARAMETER NAME="PHASE" VALUE="0.0"/>
          <PARAMETER NAME="CLK_DOMAIN" VALUE="system_pll_0_0_clk_out1"/>
          <PARAMETER NAME="LAYERED_METADATA" VALUE="undef"/>
          <PARAMETER NAME="INSERT_VIP" VALUE="0"/>
          <PORTMAPS>
            <PORTMAP LOGICAL="TDATA" PHYSICAL="m01_axis_tdata"/>
            <PORTMAP LOGICAL="TVALID" PHYSICAL="m01_axis_tvalid"/>
            <PORTMAP LOGICAL="TREADY" PHYSICAL="m01_axis_tready"/>
          </PORTMAPS>
        </BUSINTERFACE>
        <BUSINTERFACE BUSNAME="__NOC__" NAME="m02_axis" TYPE="INITIATOR" VLNV="xilinx.com:interface:axis:1.0">
          <PARAMETER NAME="TDATA_NUM_BYTES" VALUE="4"/>
          <PARAMETER NAME="TDEST_WIDTH" VALUE="0"/>
          <PARAMETER NAME="TID_WIDTH" VALUE="0"/>
          <PARAMETER NAME="TUSER_WIDTH" VALUE="0"/>
          <PARAMETER NAME="HAS_TREADY" VALUE="1"/>
          <PARAMETER NAME="HAS_TSTRB" VALUE="0"/>
          <PARAMETER NAME="HAS_TKEEP" VALUE="0"/>
          <PARAMETER NAME="HAS_TLAST" VALUE="0"/>
          <PARAMETER NAME="FREQ_HZ" VALUE="122880000"/>
          <PARAMETER NAME="PHASE" VALUE="0.0"/>
          <PARAMETER NAME="CLK_DOMAIN" VALUE="system_pll_0_0_clk_out1"/>
          <PARAMETER NAME="LAYERED_METADATA" VALUE="undef"/>
          <PARAMETER NAME="INSERT_VIP" VALUE="0"/>
          <PORTMAPS>
            <PORTMAP LOGICAL="TDATA" PHYSICAL="m02_axis_tdata"/>
            <PORTMAP LOGICAL="TVALID" PHYSICAL="m02_axis_tvalid"/>
            <PORTMAP LOGICAL="TREADY" PHYSICAL="m02_axis_tready"/>
          </PORTMAPS>
        </BUSINTERFACE>
        <BUSINTERFACE BUSNAME="__NOC__" NAME="m03_axis" TYPE="INITIATOR" VLNV="xilinx.com:interface:axis:1.0">
          <PARAMETER NAME="TDATA_NUM_BYTES" VALUE="4"/>
          <PARAMETER NAME="TDEST_WIDTH" VALUE="0"/>
          <PARAMETER NAME="TID_WIDTH" VALUE="0"/>
          <PARAMETER NAME="TUSER_WIDTH" VALUE="0"/>
          <PARAMETER NAME="HAS_TREADY" VALUE="1"/>
          <PARAMETER NAME="HAS_TSTRB" VALUE="0"/>
          <PARAMETER NAME="HAS_TKEEP" VALUE="0"/>
          <PARAMETER NAME="HAS_TLAST" VALUE="0"/>
          <PARAMETER NAME="FREQ_HZ" VALUE="122880000"/>
          <PARAMETER NAME="PHASE" VALUE="0.0"/>
          <PARAMETER NAME="CLK_DOMAIN" VALUE="system_pll_0_0_clk_out1"/>
          <PARAMETER NAME="LAYERED_METADATA" VALUE="undef"/>
          <PARAMETER NAME="INSERT_VIP" VALUE="0"/>
          <PORTMAPS>
            <PORTMAP LOGICAL="TDATA" PHYSICAL="m03_axis_tdata"/>
            <PORTMAP LOGICAL="TVALID" PHYSICAL="m03_axis_tvalid"/>
            <PORTMAP LOGICAL="TREADY" PHYSICAL="m03_axis_tready"/>
          </PORTMAPS>
        </BUSINTERFACE>
        <BUSINTERFACE BUSNAME="__NOC__" NAME="m04_axis" TYPE="INITIATOR" VLNV="xilinx.com:interface:axis:1.0">
          <PARAMETER NAME="TDATA_NUM_BYTES" VALUE="4"/>
          <PARAMETER NAME="TDEST_WIDTH" VALUE="0"/>
          <PARAMETER NAME="TID_WIDTH" VALUE="0"/>
          <PARAMETER NAME="TUSER_WIDTH" VALUE="0"/>
          <PARAMETER NAME="HAS_TREADY" VALUE="1"/>
          <PARAMETER NAME="HAS_TSTRB" VALUE="0"/>
          <PARAMETER NAME="HAS_TKEEP" VALUE="0"/>
          <PARAMETER NAME="HAS_TLAST" VALUE="0"/>
          <PARAMETER NAME="FREQ_HZ" VALUE="122880000"/>
          <PARAMETER NAME="PHASE" VALUE="0.0"/>
          <PARAMETER NAME="CLK_DOMAIN" VALUE="system_pll_0_0_clk_out1"/>
          <PARAMETER NAME="LAYERED_METADATA" VALUE="undef"/>
          <PARAMETER NAME="INSERT_VIP" VALUE="0"/>
          <PORTMAPS>
            <PORTMAP LOGICAL="TDATA" PHYSICAL="m04_axis_tdata"/>
            <PORTMAP LOGICAL="TVALID" PHYSICAL="m04_axis_tvalid"/>
            <PORTMAP LOGICAL="TREADY" PHYSICAL="m04_axis_tready"/>
          </PORTMAPS>
        </BUSINTERFACE>
        <BUSINTERFACE BUSNAME="__NOC__" NAME="m05_axis" TYPE="INITIATOR" VLNV="xilinx.com:interface:axis:1.0">
          <PARAMETER NAME="TDATA_NUM_BYTES" VALUE="4"/>
          <PARAMETER NAME="TDEST_WIDTH" VALUE="0"/>
          <PARAMETER NAME="TID_WIDTH" VALUE="0"/>
          <PARAMETER NAME="TUSER_WIDTH" VALUE="0"/>
          <PARAMETER NAME="HAS_TREADY" VALUE="1"/>
          <PARAMETER NAME="HAS_TSTRB" VALUE="0"/>
          <PARAMETER NAME="HAS_TKEEP" VALUE="0"/>
          <PARAMETER NAME="HAS_TLAST" VALUE="0"/>
          <PARAMETER NAME="FREQ_HZ" VALUE="122880000"/>
          <PARAMETER NAME="PHASE" VALUE="0.0"/>
          <PARAMETER NAME="CLK_DOMAIN" VALUE="system_pll_0_0_clk_out1"/>
          <PARAMETER NAME="LAYERED_METADATA" VALUE="undef"/>
          <PARAMETER NAME="INSERT_VIP" VALUE="0"/>
          <PORTMAPS>
            <PORTMAP LOGICAL="TDATA" PHYSICAL="m05_axis_tdata"/>
            <PORTMAP LOGICAL="TVALID" PHYSICAL="m05_axis_tvalid"/>
            <PORTMAP LOGICAL="TREADY" PHYSICAL="m05_axis_tready"/>
          </PORTMAPS>
        </BUSINTERFACE>
        <BUSINTERFACE BUSNAME="__NOC__" NAME="s00_axis" TYPE="TARGET" VLNV="xilinx.com:interface:axis:1.0">
          <PARAMETER NAME="TDATA_NUM_BYTES" VALUE="4"/>
          <PARAMETER NAME="TDEST_WIDTH" VALUE="0"/>
          <PARAMETER NAME="TID_WIDTH" VALUE="0"/>
          <PARAMETER NAME="TUSER_WIDTH" VALUE="0"/>
          <PARAMETER NAME="HAS_TREADY" VALUE="1"/>
          <PARAMETER NAME="HAS_TSTRB" VALUE="0"/>
          <PARAMETER NAME="HAS_TKEEP" VALUE="0"/>
          <PARAMETER NAME="HAS_TLAST" VALUE="0"/>
          <PARAMETER NAME="FREQ_HZ" VALUE="122880000"/>
          <PARAMETER NAME="PHASE" VALUE="0.0"/>
          <PARAMETER NAME="CLK_DOMAIN" VALUE="system_pll_0_0_clk_out1"/>
          <PARAMETER NAME="LAYERED_METADATA" VALUE="undef"/>
          <PARAMETER NAME="INSERT_VIP" VALUE="0"/>
          <PORTMAPS>
            <PORTMAP LOGICAL="TDATA" PHYSICAL="s00_axis_tdata"/>
            <PORTMAP LOGICAL="TVALID" PHYSICAL="s00_axis_tvalid"/>
            <PORTMAP LOGICAL="TREADY" PHYSICAL="s00_axis_tready"/>
          </PORTMAPS>
        </BUSINTERFACE>
        <BUSINTERFACE BUSNAME="__NOC__" NAME="s01_axis" TYPE="TARGET" VLNV="xilinx.com:interface:axis:1.0">
          <PARAMETER NAME="TDATA_NUM_BYTES" VALUE="4"/>
          <PARAMETER NAME="TDEST_WIDTH" VALUE="0"/>
          <PARAMETER NAME="TID_WIDTH" VALUE="0"/>
          <PARAMETER NAME="TUSER_WIDTH" VALUE="0"/>
          <PARAMETER NAME="HAS_TREADY" VALUE="1"/>
          <PARAMETER NAME="HAS_TSTRB" VALUE="0"/>
          <PARAMETER NAME="HAS_TKEEP" VALUE="0"/>
          <PARAMETER NAME="HAS_TLAST" VALUE="0"/>
          <PARAMETER NAME="FREQ_HZ" VALUE="122880000"/>
          <PARAMETER NAME="PHASE" VALUE="0.0"/>
          <PARAMETER NAME="CLK_DOMAIN" VALUE="system_pll_0_0_clk_out1"/>
          <PARAMETER NAME="LAYERED_METADATA" VALUE="undef"/>
          <PARAMETER NAME="INSERT_VIP" VALUE="0"/>
          <PORTMAPS>
            <PORTMAP LOGICAL="TDATA" PHYSICAL="s01_axis_tdata"/>
            <PORTMAP LOGICAL="TVALID" PHYSICAL="s01_axis_tvalid"/>
            <PORTMAP LOGICAL="TREADY" PHYSICAL="s01_axis_tready"/>
          </PORTMAPS>
        </BUSINTERFACE>
        <BUSINTERFACE BUSNAME="__NOC__" NAME="s02_axis" TYPE="TARGET" VLNV="xilinx.com:interface:axis:1.0">
          <PARAMETER NAME="TDATA_NUM_BYTES" VALUE="4"/>
          <PARAMETER NAME="TDEST_WIDTH" VALUE="0"/>
          <PARAMETER NAME="TID_WIDTH" VALUE="0"/>
          <PARAMETER NAME="TUSER_WIDTH" VALUE="0"/>
          <PARAMETER NAME="HAS_TREADY" VALUE="1"/>
          <PARAMETER NAME="HAS_TSTRB" VALUE="0"/>
          <PARAMETER NAME="HAS_TKEEP" VALUE="0"/>
          <PARAMETER NAME="HAS_TLAST" VALUE="0"/>
          <PARAMETER NAME="FREQ_HZ" VALUE="122880000"/>
          <PARAMETER NAME="PHASE" VALUE="0.0"/>
          <PARAMETER NAME="CLK_DOMAIN" VALUE="system_pll_0_0_clk_out1"/>
          <PARAMETER NAME="LAYERED_METADATA" VALUE="undef"/>
          <PARAMETER NAME="INSERT_VIP" VALUE="0"/>
          <PORTMAPS>
            <PORTMAP LOGICAL="TDATA" PHYSICAL="s02_axis_tdata"/>
            <PORTMAP LOGICAL="TVALID" PHYSICAL="s02_axis_tvalid"/>
            <PORTMAP LOGICAL="TREADY" PHYSICAL="s02_axis_tready"/>
          </PORTMAPS>
        </BUSINTERFACE>
        <BUSINTERFACE BUSNAME="__NOC__" NAME="s03_axis" TYPE="TARGET" VLNV="xilinx.com:interface:axis:1.0">
          <PARAMETER NAME="TDATA_NUM_BYTES" VALUE="4"/>
          <PARAMETER NAME="TDEST_WIDTH" VALUE="0"/>
          <PARAMETER NAME="TID_WIDTH" VALUE="0"/>
          <PARAMETER NAME="TUSER_WIDTH" VALUE="0"/>
          <PARAMETER NAME="HAS_TREADY" VALUE="1"/>
          <PARAMETER NAME="HAS_TSTRB" VALUE="0"/>
          <PARAMETER NAME="HAS_TKEEP" VALUE="0"/>
          <PARAMETER NAME="HAS_TLAST" VALUE="0"/>
          <PARAMETER NAME="FREQ_HZ" VALUE="122880000"/>
          <PARAMETER NAME="PHASE" VALUE="0.0"/>
          <PARAMETER NAME="CLK_DOMAIN" VALUE="system_pll_0_0_clk_out1"/>
          <PARAMETER NAME="LAYERED_METADATA" VALUE="undef"/>
          <PARAMETER NAME="INSERT_VIP" VALUE="0"/>
          <PORTMAPS>
            <PORTMAP LOGICAL="TDATA" PHYSICAL="s03_axis_tdata"/>
            <PORTMAP LOGICAL="TVALID" PHYSICAL="s03_axis_tvalid"/>
            <PORTMAP LOGICAL="TREADY" PHYSICAL="s03_axis_tready"/>
          </PORTMAPS>
        </BUSINTERFACE>
        <BUSINTERFACE BUSNAME="__NOC__" NAME="s04_axis" TYPE="TARGET" VLNV="xilinx.com:interface:axis:1.0">
          <PARAMETER NAME="TDATA_NUM_BYTES" VALUE="4"/>
          <PARAMETER NAME="TDEST_WIDTH" VALUE="0"/>
          <PARAMETER NAME="TID_WIDTH" VALUE="0"/>
          <PARAMETER NAME="TUSER_WIDTH" VALUE="0"/>
          <PARAMETER NAME="HAS_TREADY" VALUE="1"/>
          <PARAMETER NAME="HAS_TSTRB" VALUE="0"/>
          <PARAMETER NAME="HAS_TKEEP" VALUE="0"/>
          <PARAMETER NAME="HAS_TLAST" VALUE="0"/>
          <PARAMETER NAME="FREQ_HZ" VALUE="122880000"/>
          <PARAMETER NAME="PHASE" VALUE="0.0"/>
          <PARAMETER NAME="CLK_DOMAIN" VALUE="system_pll_0_0_clk_out1"/>
          <PARAMETER NAME="LAYERED_METADATA" VALUE="undef"/>
          <PARAMETER NAME="INSERT_VIP" VALUE="0"/>
          <PORTMAPS>
            <PORTMAP LOGICAL="TDATA" PHYSICAL="s04_axis_tdata"/>
            <PORTMAP LOGICAL="TVALID" PHYSICAL="s04_axis_tvalid"/>
            <PORTMAP LOGICAL="TREADY" PHYSICAL="s04_axis_tready"/>
          </PORTMAPS>
        </BUSINTERFACE>
        <BUSINTERFACE BUSNAME="__NOC__" NAME="s05_axis" TYPE="TARGET" VLNV="xilinx.com:interface:axis:1.0">
          <PARAMETER NAME="TDATA_NUM_BYTES" VALUE="4"/>
          <PARAMETER NAME="TDEST_WIDTH" VALUE="0"/>
          <PARAMETER NAME="TID_WIDTH" VALUE="0"/>
          <PARAMETER NAME="TUSER_WIDTH" VALUE="0"/>
          <PARAMETER NAME="HAS_TREADY" VALUE="1"/>
          <PARAMETER NAME="HAS_TSTRB" VALUE="0"/>
          <PARAMETER NAME="HAS_TKEEP" VALUE="0"/>
          <PARAMETER NAME="HAS_TLAST" VALUE="0"/>
          <PARAMETER NAME="FREQ_HZ" VALUE="122880000"/>
          <PARAMETER NAME="PHASE" VALUE="0.0"/>
          <PARAMETER NAME="CLK_DOMAIN" VALUE="system_pll_0_0_clk_out1"/>
          <PARAMETER NAME="LAYERED_METADATA" VALUE="undef"/>
          <PARAMETER NAME="INSERT_VIP" VALUE="0"/>
          <PORTMAPS>
            <PORTMAP LOGICAL="TDATA" PHYSICAL="s05_axis_tdata"/>
            <PORTMAP LOGICAL="TVALID" PHYSICAL="s05_axis_tvalid"/>
            <PORTMAP LOGICAL="TREADY" PHYSICAL="s05_axis_tready"/>
          </PORTMAPS>
        </BUSINTERFACE>
        <BUSINTERFACE BUSNAME="ps_0_M_AXI_GP0" DATAWIDTH="32" NAME="s_axi" TYPE="SLAVE" VLNV="xilinx.com:interface:aximm:1.0">
          <PARAMETER NAME="DATA_WIDTH" VALUE="32"/>
          <PARAMETER NAME="PROTOCOL" VALUE="AXI3"/>
          <PARAMETER NAME="FREQ_HZ" VALUE="122880000"/>
          <PARAMETER NAME="ID_WIDTH" VALUE="12"/>
          <PARAMETER NAME="ADDR_WIDTH" VALUE="32"/>
          <PARAMETER NAME="AWUSER_WIDTH" VALUE="0"/>
          <PARAMETER NAME="ARUSER_WIDTH" VALUE="0"/>
          <PARAMETER NAME="WUSER_WIDTH" VALUE="0"/>
          <PARAMETER NAME="RUSER_WIDTH" VALUE="0"/>
          <PARAMETER NAME="BUSER_WIDTH" VALUE="0"/>
          <PARAMETER NAME="READ_WRITE_MODE" VALUE="READ_WRITE"/>
          <PARAMETER NAME="HAS_BURST" VALUE="0"/>
          <PARAMETER NAME="HAS_LOCK" VALUE="0"/>
          <PARAMETER NAME="HAS_PROT" VALUE="0"/>
          <PARAMETER NAME="HAS_CACHE" VALUE="0"/>
          <PARAMETER NAME="HAS_QOS" VALUE="0"/>
          <PARAMETER NAME="HAS_REGION" VALUE="0"/>
          <PARAMETER NAME="HAS_WSTRB" VALUE="1"/>
          <PARAMETER NAME="HAS_BRESP" VALUE="0"/>
          <PARAMETER NAME="HAS_RRESP" VALUE="0"/>
          <PARAMETER NAME="SUPPORTS_NARROW_BURST" VALUE="0"/>
          <PARAMETER NAME="NUM_READ_OUTSTANDING" VALUE="2"/>
          <PARAMETER NAME="NUM_WRITE_OUTSTANDING" VALUE="2"/>
          <PARAMETER NAME="MAX_BURST_LENGTH" VALUE="16"/>
          <PARAMETER NAME="PHASE" VALUE="0.0"/>
          <PARAMETER NAME="CLK_DOMAIN" VALUE="system_pll_0_0_clk_out1"/>
          <PARAMETER NAME="NUM_READ_THREADS" VALUE="4"/>
          <PARAMETER NAME="NUM_WRITE_THREADS" VALUE="4"/>
          <PARAMETER NAME="RUSER_BITS_PER_BYTE" VALUE="0"/>
          <PARAMETER NAME="WUSER_BITS_PER_BYTE" VALUE="0"/>
          <PARAMETER NAME="INSERT_VIP" VALUE="0"/>
          <PORTMAPS>
            <PORTMAP LOGICAL="AWID" PHYSICAL="s_axi_awid"/>
            <PORTMAP LOGICAL="AWADDR" PHYSICAL="s_axi_awaddr"/>
            <PORTMAP LOGICAL="AWVALID" PHYSICAL="s_axi_awvalid"/>
            <PORTMAP LOGICAL="AWREADY" PHYSICAL="s_axi_awready"/>
            <PORTMAP LOGICAL="WDATA" PHYSICAL="s_axi_wdata"/>
            <PORTMAP LOGICAL="WSTRB" PHYSICAL="s_axi_wstrb"/>
            <PORTMAP LOGICAL="WLAST" PHYSICAL="s_axi_wlast"/>
            <PORTMAP LOGICAL="WVALID" PHYSICAL="s_axi_wvalid"/>
            <PORTMAP LOGICAL="WREADY" PHYSICAL="s_axi_wready"/>
            <PORTMAP LOGICAL="BID" PHYSICAL="s_axi_bid"/>
            <PORTMAP LOGICAL="BVALID" PHYSICAL="s_axi_bvalid"/>
            <PORTMAP LOGICAL="BREADY" PHYSICAL="s_axi_bready"/>
            <PORTMAP LOGICAL="ARID" PHYSICAL="s_axi_arid"/>
            <PORTMAP LOGICAL="ARADDR" PHYSICAL="s_axi_araddr"/>
            <PORTMAP LOGICAL="ARLEN" PHYSICAL="s_axi_arlen"/>
            <PORTMAP LOGICAL="ARVALID" PHYSICAL="s_axi_arvalid"/>
            <PORTMAP LOGICAL="ARREADY" PHYSICAL="s_axi_arready"/>
            <PORTMAP LOGICAL="RID" PHYSICAL="s_axi_rid"/>
            <PORTMAP LOGICAL="RDATA" PHYSICAL="s_axi_rdata"/>
            <PORTMAP LOGICAL="RLAST" PHYSICAL="s_axi_rlast"/>
            <PORTMAP LOGICAL="RVALID" PHYSICAL="s_axi_rvalid"/>
            <PORTMAP LOGICAL="RREADY" PHYSICAL="s_axi_rready"/>
          </PORTMAPS>
        </BUSINTERFACE>
      </BUSINTERFACES>
    </MODULE>
    <MODULE COREREVISION="1" FULLNAME="/io_bridge_out" HWVERSION="1.0" INSTANCE="io_bridge_out" IPTYPE="PERIPHERAL" IS_ENABLE="1" MODCLASS="PERIPHERAL" MODTYPE="exp_io_bridge" VLNV="pavel-demin:user:exp_io_bridge:1.0">
      <DOCUMENTS/>
      <PARAMETERS>
        <PARAMETER NAME="WIDTH" VALUE="8"/>
        <PARAMETER NAME="Component_Name" VALUE="system_io_bridge_out_0"/>
        <PARAMETER NAME="EDK_IPTYPE" VALUE="PERIPHERAL"/>
      </PARAMETERS>
      <PORTS>
        <PORT DIR="IO" LEFT="7" NAME="io" RIGHT="0" SIGIS="undef" SIGNAME="External_Ports_exp_n_tri_io">
          <CONNECTIONS>
            <CONNECTION INSTANCE="External_Ports" PORT="exp_n_tri_io"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" LEFT="7" NAME="out_data" RIGHT="0" SIGIS="undef" SIGNAME="slice_GPIO_out1_dout">
          <CONNECTIONS>
            <CONNECTION INSTANCE="slice_GPIO_out1" PORT="dout"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" LEFT="7" NAME="in_data" RIGHT="0" SIGIS="undef"/>
        <PORT DIR="I" LEFT="7" NAME="dir" RIGHT="0" SIGIS="undef" SIGNAME="const_GPIO_out_dout">
          <CONNECTIONS>
            <CONNECTION INSTANCE="const_GPIO_out" PORT="dout"/>
          </CONNECTIONS>
        </PORT>
      </PORTS>
      <BUSINTERFACES/>
    </MODULE>
    <MODULE COREREVISION="1" FULLNAME="/mult_0" HWVERSION="1.0" INSTANCE="mult_0" IPTYPE="PERIPHERAL" IS_ENABLE="1" MODCLASS="PERIPHERAL" MODTYPE="dsp48" VLNV="pavel-demin:user:dsp48:1.0">
      <DOCUMENTS/>
      <PARAMETERS>
        <PARAMETER NAME="A_WIDTH" VALUE="24"/>
        <PARAMETER NAME="B_WIDTH" VALUE="16"/>
        <PARAMETER NAME="P_WIDTH" VALUE="24"/>
        <PARAMETER NAME="Component_Name" VALUE="system_mult_0_0"/>
        <PARAMETER NAME="EDK_IPTYPE" VALUE="PERIPHERAL"/>
      </PARAMETERS>
      <PORTS>
        <PORT CLKFREQUENCY="122880000" DIR="I" NAME="CLK" SIGIS="clk" SIGNAME="pll_0_clk_out1">
          <CONNECTIONS>
            <CONNECTION INSTANCE="pll_0" PORT="clk_out1"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" LEFT="23" NAME="A" RIGHT="0" SIGIS="undef" SIGNAME="dds_slice_0_dout">
          <CONNECTIONS>
            <CONNECTION INSTANCE="dds_slice_0" PORT="dout"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" LEFT="15" NAME="B" RIGHT="0" SIGIS="undef" SIGNAME="adc_slice_0_dout">
          <CONNECTIONS>
            <CONNECTION INSTANCE="adc_slice_0" PORT="dout"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" LEFT="23" NAME="P" RIGHT="0" SIGIS="undef" SIGNAME="mult_0_P">
          <CONNECTIONS>
            <CONNECTION INSTANCE="cic_0" PORT="s_axis_data_tdata"/>
          </CONNECTIONS>
        </PORT>
      </PORTS>
      <BUSINTERFACES/>
    </MODULE>
    <MODULE COREREVISION="1" FULLNAME="/mult_1" HWVERSION="1.0" INSTANCE="mult_1" IPTYPE="PERIPHERAL" IS_ENABLE="1" MODCLASS="PERIPHERAL" MODTYPE="dsp48" VLNV="pavel-demin:user:dsp48:1.0">
      <DOCUMENTS/>
      <PARAMETERS>
        <PARAMETER NAME="A_WIDTH" VALUE="24"/>
        <PARAMETER NAME="B_WIDTH" VALUE="16"/>
        <PARAMETER NAME="P_WIDTH" VALUE="24"/>
        <PARAMETER NAME="Component_Name" VALUE="system_mult_1_0"/>
        <PARAMETER NAME="EDK_IPTYPE" VALUE="PERIPHERAL"/>
      </PARAMETERS>
      <PORTS>
        <PORT CLKFREQUENCY="122880000" DIR="I" NAME="CLK" SIGIS="clk" SIGNAME="pll_0_clk_out1">
          <CONNECTIONS>
            <CONNECTION INSTANCE="pll_0" PORT="clk_out1"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" LEFT="23" NAME="A" RIGHT="0" SIGIS="undef" SIGNAME="dds_slice_1_dout">
          <CONNECTIONS>
            <CONNECTION INSTANCE="dds_slice_1" PORT="dout"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" LEFT="15" NAME="B" RIGHT="0" SIGIS="undef" SIGNAME="adc_slice_1_dout">
          <CONNECTIONS>
            <CONNECTION INSTANCE="adc_slice_1" PORT="dout"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" LEFT="23" NAME="P" RIGHT="0" SIGIS="undef" SIGNAME="mult_1_P">
          <CONNECTIONS>
            <CONNECTION INSTANCE="cic_1" PORT="s_axis_data_tdata"/>
          </CONNECTIONS>
        </PORT>
      </PORTS>
      <BUSINTERFACES/>
    </MODULE>
    <MODULE COREREVISION="1" FULLNAME="/mult_2" HWVERSION="1.0" INSTANCE="mult_2" IPTYPE="PERIPHERAL" IS_ENABLE="1" MODCLASS="PERIPHERAL" MODTYPE="dsp48" VLNV="pavel-demin:user:dsp48:1.0">
      <DOCUMENTS/>
      <PARAMETERS>
        <PARAMETER NAME="A_WIDTH" VALUE="24"/>
        <PARAMETER NAME="B_WIDTH" VALUE="16"/>
        <PARAMETER NAME="P_WIDTH" VALUE="24"/>
        <PARAMETER NAME="Component_Name" VALUE="system_mult_2_0"/>
        <PARAMETER NAME="EDK_IPTYPE" VALUE="PERIPHERAL"/>
      </PARAMETERS>
      <PORTS>
        <PORT CLKFREQUENCY="122880000" DIR="I" NAME="CLK" SIGIS="clk" SIGNAME="pll_0_clk_out1">
          <CONNECTIONS>
            <CONNECTION INSTANCE="pll_0" PORT="clk_out1"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" LEFT="23" NAME="A" RIGHT="0" SIGIS="undef" SIGNAME="dds_slice_2_dout">
          <CONNECTIONS>
            <CONNECTION INSTANCE="dds_slice_2" PORT="dout"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" LEFT="15" NAME="B" RIGHT="0" SIGIS="undef" SIGNAME="adc_slice_2_dout">
          <CONNECTIONS>
            <CONNECTION INSTANCE="adc_slice_2" PORT="dout"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" LEFT="23" NAME="P" RIGHT="0" SIGIS="undef" SIGNAME="mult_2_P">
          <CONNECTIONS>
            <CONNECTION INSTANCE="cic_2" PORT="s_axis_data_tdata"/>
          </CONNECTIONS>
        </PORT>
      </PORTS>
      <BUSINTERFACES/>
    </MODULE>
    <MODULE COREREVISION="1" FULLNAME="/mult_3" HWVERSION="1.0" INSTANCE="mult_3" IPTYPE="PERIPHERAL" IS_ENABLE="1" MODCLASS="PERIPHERAL" MODTYPE="dsp48" VLNV="pavel-demin:user:dsp48:1.0">
      <DOCUMENTS/>
      <PARAMETERS>
        <PARAMETER NAME="A_WIDTH" VALUE="24"/>
        <PARAMETER NAME="B_WIDTH" VALUE="16"/>
        <PARAMETER NAME="P_WIDTH" VALUE="24"/>
        <PARAMETER NAME="Component_Name" VALUE="system_mult_3_0"/>
        <PARAMETER NAME="EDK_IPTYPE" VALUE="PERIPHERAL"/>
      </PARAMETERS>
      <PORTS>
        <PORT CLKFREQUENCY="122880000" DIR="I" NAME="CLK" SIGIS="clk" SIGNAME="pll_0_clk_out1">
          <CONNECTIONS>
            <CONNECTION INSTANCE="pll_0" PORT="clk_out1"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" LEFT="23" NAME="A" RIGHT="0" SIGIS="undef" SIGNAME="dds_slice_3_dout">
          <CONNECTIONS>
            <CONNECTION INSTANCE="dds_slice_3" PORT="dout"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" LEFT="15" NAME="B" RIGHT="0" SIGIS="undef" SIGNAME="adc_slice_3_dout">
          <CONNECTIONS>
            <CONNECTION INSTANCE="adc_slice_3" PORT="dout"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" LEFT="23" NAME="P" RIGHT="0" SIGIS="undef" SIGNAME="mult_3_P">
          <CONNECTIONS>
            <CONNECTION INSTANCE="cic_3" PORT="s_axis_data_tdata"/>
          </CONNECTIONS>
        </PORT>
      </PORTS>
      <BUSINTERFACES/>
    </MODULE>
    <MODULE COREREVISION="1" FULLNAME="/mult_4" HWVERSION="1.0" INSTANCE="mult_4" IPTYPE="PERIPHERAL" IS_ENABLE="1" MODCLASS="PERIPHERAL" MODTYPE="dsp48" VLNV="pavel-demin:user:dsp48:1.0">
      <DOCUMENTS/>
      <PARAMETERS>
        <PARAMETER NAME="A_WIDTH" VALUE="24"/>
        <PARAMETER NAME="B_WIDTH" VALUE="16"/>
        <PARAMETER NAME="P_WIDTH" VALUE="14"/>
        <PARAMETER NAME="Component_Name" VALUE="system_mult_4_0"/>
        <PARAMETER NAME="EDK_IPTYPE" VALUE="PERIPHERAL"/>
      </PARAMETERS>
      <PORTS>
        <PORT CLKFREQUENCY="122880000" DIR="I" NAME="CLK" SIGIS="clk" SIGNAME="pll_0_clk_out1">
          <CONNECTIONS>
            <CONNECTION INSTANCE="pll_0" PORT="clk_out1"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" LEFT="23" NAME="A" RIGHT="0" SIGIS="undef" SIGNAME="dds_2_dout">
          <CONNECTIONS>
            <CONNECTION INSTANCE="dds_2" PORT="dout"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" LEFT="15" NAME="B" RIGHT="0" SIGIS="undef" SIGNAME="slice_8_dout">
          <CONNECTIONS>
            <CONNECTION INSTANCE="slice_8" PORT="dout"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" LEFT="13" NAME="P" RIGHT="0" SIGIS="undef" SIGNAME="mult_4_P">
          <CONNECTIONS>
            <CONNECTION INSTANCE="concat_0" PORT="In0"/>
          </CONNECTIONS>
        </PORT>
      </PORTS>
      <BUSINTERFACES/>
    </MODULE>
    <MODULE COREREVISION="1" FULLNAME="/mult_5" HWVERSION="1.0" INSTANCE="mult_5" IPTYPE="PERIPHERAL" IS_ENABLE="1" MODCLASS="PERIPHERAL" MODTYPE="dsp48" VLNV="pavel-demin:user:dsp48:1.0">
      <DOCUMENTS/>
      <PARAMETERS>
        <PARAMETER NAME="A_WIDTH" VALUE="24"/>
        <PARAMETER NAME="B_WIDTH" VALUE="16"/>
        <PARAMETER NAME="P_WIDTH" VALUE="14"/>
        <PARAMETER NAME="Component_Name" VALUE="system_mult_5_0"/>
        <PARAMETER NAME="EDK_IPTYPE" VALUE="PERIPHERAL"/>
      </PARAMETERS>
      <PORTS>
        <PORT CLKFREQUENCY="122880000" DIR="I" NAME="CLK" SIGIS="clk" SIGNAME="pll_0_clk_out1">
          <CONNECTIONS>
            <CONNECTION INSTANCE="pll_0" PORT="clk_out1"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" LEFT="23" NAME="A" RIGHT="0" SIGIS="undef" SIGNAME="dds_3_dout">
          <CONNECTIONS>
            <CONNECTION INSTANCE="dds_3" PORT="dout"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" LEFT="15" NAME="B" RIGHT="0" SIGIS="undef" SIGNAME="dds_3_dout">
          <CONNECTIONS>
            <CONNECTION INSTANCE="dds_3" PORT="dout"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" LEFT="13" NAME="P" RIGHT="0" SIGIS="undef" SIGNAME="mult_5_P">
          <CONNECTIONS>
            <CONNECTION INSTANCE="concat_0" PORT="In1"/>
          </CONNECTIONS>
        </PORT>
      </PORTS>
      <BUSINTERFACES/>
    </MODULE>
    <MODULE COREREVISION="9" FULLNAME="/pll_0" HWVERSION="6.0" INSTANCE="pll_0" IPTYPE="PERIPHERAL" IS_ENABLE="1" MODCLASS="PERIPHERAL" MODTYPE="clk_wiz" VLNV="xilinx.com:ip:clk_wiz:6.0">
      <DOCUMENTS>
        <DOCUMENT SOURCE="http://www.xilinx.com/cgi-bin/docs/ipdoc?c=clk_wiz;v=v6_0;d=pg065-clk-wiz.pdf"/>
      </DOCUMENTS>
      <PARAMETERS>
        <PARAMETER NAME="C_CLKOUT2_USED" VALUE="1"/>
        <PARAMETER NAME="C_USER_CLK_FREQ0" VALUE="100.0"/>
        <PARAMETER NAME="C_AUTO_PRIMITIVE" VALUE="MMCM"/>
        <PARAMETER NAME="C_USER_CLK_FREQ1" VALUE="100.0"/>
        <PARAMETER NAME="C_USER_CLK_FREQ2" VALUE="100.0"/>
        <PARAMETER NAME="C_USER_CLK_FREQ3" VALUE="100.0"/>
        <PARAMETER NAME="C_ENABLE_CLOCK_MONITOR" VALUE="0"/>
        <PARAMETER NAME="C_ENABLE_USER_CLOCK0" VALUE="0"/>
        <PARAMETER NAME="C_ENABLE_USER_CLOCK1" VALUE="0"/>
        <PARAMETER NAME="C_ENABLE_USER_CLOCK2" VALUE="0"/>
        <PARAMETER NAME="C_ENABLE_USER_CLOCK3" VALUE="0"/>
        <PARAMETER NAME="C_Enable_PLL0" VALUE="0"/>
        <PARAMETER NAME="C_Enable_PLL1" VALUE="0"/>
        <PARAMETER NAME="C_REF_CLK_FREQ" VALUE="100.0"/>
        <PARAMETER NAME="C_PRECISION" VALUE="1"/>
        <PARAMETER NAME="C_CLKOUT3_USED" VALUE="1"/>
        <PARAMETER NAME="C_CLKOUT4_USED" VALUE="0"/>
        <PARAMETER NAME="C_CLKOUT5_USED" VALUE="0"/>
        <PARAMETER NAME="C_CLKOUT6_USED" VALUE="0"/>
        <PARAMETER NAME="C_CLKOUT7_USED" VALUE="0"/>
        <PARAMETER NAME="C_USE_CLKOUT1_BAR" VALUE="0"/>
        <PARAMETER NAME="C_USE_CLKOUT2_BAR" VALUE="0"/>
        <PARAMETER NAME="C_USE_CLKOUT3_BAR" VALUE="0"/>
        <PARAMETER NAME="C_USE_CLKOUT4_BAR" VALUE="0"/>
        <PARAMETER NAME="c_component_name" VALUE="system_pll_0_0"/>
        <PARAMETER NAME="C_PLATFORM" VALUE="UNKNOWN"/>
        <PARAMETER NAME="C_USE_FREQ_SYNTH" VALUE="1"/>
        <PARAMETER NAME="C_USE_PHASE_ALIGNMENT" VALUE="1"/>
        <PARAMETER NAME="C_PRIM_IN_JITTER" VALUE="0.010"/>
        <PARAMETER NAME="C_SECONDARY_IN_JITTER" VALUE="0.010"/>
        <PARAMETER NAME="C_JITTER_SEL" VALUE="No_Jitter"/>
        <PARAMETER NAME="C_USE_MIN_POWER" VALUE="0"/>
        <PARAMETER NAME="C_USE_MIN_O_JITTER" VALUE="0"/>
        <PARAMETER NAME="C_USE_MAX_I_JITTER" VALUE="0"/>
        <PARAMETER NAME="C_USE_DYN_PHASE_SHIFT" VALUE="0"/>
        <PARAMETER NAME="C_OPTIMIZE_CLOCKING_STRUCTURE_EN" VALUE="0"/>
        <PARAMETER NAME="C_USE_INCLK_SWITCHOVER" VALUE="0"/>
        <PARAMETER NAME="C_USE_DYN_RECONFIG" VALUE="0"/>
        <PARAMETER NAME="C_USE_SPREAD_SPECTRUM" VALUE="0"/>
        <PARAMETER NAME="C_USE_FAST_SIMULATION" VALUE="0"/>
        <PARAMETER NAME="C_PRIMTYPE_SEL" VALUE="AUTO"/>
        <PARAMETER NAME="C_USE_CLK_VALID" VALUE="0"/>
        <PARAMETER NAME="C_PRIM_IN_FREQ" VALUE="122.88"/>
        <PARAMETER NAME="C_PRIM_IN_TIMEPERIOD" VALUE="10.000"/>
        <PARAMETER NAME="C_IN_FREQ_UNITS" VALUE="Units_MHz"/>
        <PARAMETER NAME="C_SECONDARY_IN_FREQ" VALUE="100.000"/>
        <PARAMETER NAME="C_SECONDARY_IN_TIMEPERIOD" VALUE="10.000"/>
        <PARAMETER NAME="C_FEEDBACK_SOURCE" VALUE="FDBK_AUTO"/>
        <PARAMETER NAME="C_PRIM_SOURCE" VALUE="Differential_clock_capable_pin"/>
        <PARAMETER NAME="C_PHASESHIFT_MODE" VALUE="WAVEFORM"/>
        <PARAMETER NAME="C_SECONDARY_SOURCE" VALUE="Single_ended_clock_capable_pin"/>
        <PARAMETER NAME="C_CLKFB_IN_SIGNALING" VALUE="SINGLE"/>
        <PARAMETER NAME="C_USE_RESET" VALUE="0"/>
        <PARAMETER NAME="C_RESET_LOW" VALUE="0"/>
        <PARAMETER NAME="C_USE_LOCKED" VALUE="1"/>
        <PARAMETER NAME="C_USE_INCLK_STOPPED" VALUE="0"/>
        <PARAMETER NAME="C_USE_CLKFB_STOPPED" VALUE="0"/>
        <PARAMETER NAME="C_USE_POWER_DOWN" VALUE="0"/>
        <PARAMETER NAME="C_USE_STATUS" VALUE="0"/>
        <PARAMETER NAME="C_USE_FREEZE" VALUE="0"/>
        <PARAMETER NAME="C_NUM_OUT_CLKS" VALUE="3"/>
        <PARAMETER NAME="C_CLKOUT1_DRIVES" VALUE="BUFG"/>
        <PARAMETER NAME="C_CLKOUT2_DRIVES" VALUE="BUFG"/>
        <PARAMETER NAME="C_CLKOUT3_DRIVES" VALUE="BUFG"/>
        <PARAMETER NAME="C_CLKOUT4_DRIVES" VALUE="BUFG"/>
        <PARAMETER NAME="C_CLKOUT5_DRIVES" VALUE="BUFG"/>
        <PARAMETER NAME="C_CLKOUT6_DRIVES" VALUE="BUFG"/>
        <PARAMETER NAME="C_CLKOUT7_DRIVES" VALUE="BUFG"/>
        <PARAMETER NAME="C_INCLK_SUM_ROW0" VALUE="Input Clock   Freq (MHz)    Input Jitter (UI)"/>
        <PARAMETER NAME="C_INCLK_SUM_ROW1" VALUE="__primary__________122.88____________0.010"/>
        <PARAMETER NAME="C_INCLK_SUM_ROW2" VALUE="no_secondary_input_clock"/>
        <PARAMETER NAME="C_OUTCLK_SUM_ROW0A" VALUE="Output     Output      Phase    Duty Cycle   Pk-to-Pk     Phase"/>
        <PARAMETER NAME="C_OUTCLK_SUM_ROW0B" VALUE="Clock     Freq (MHz)  (degrees)    (%)     Jitter (ps)  Error (ps)"/>
        <PARAMETER NAME="C_OUTCLK_SUM_ROW1" VALUE="clk_out1__122.88000______0.000______50.0______121.076_____98.137"/>
        <PARAMETER NAME="C_OUTCLK_SUM_ROW2" VALUE="clk_out2__245.76000____157.500______50.0______106.280_____98.137"/>
        <PARAMETER NAME="C_OUTCLK_SUM_ROW3" VALUE="clk_out3__245.76000____202.500______50.0______106.280_____98.137"/>
        <PARAMETER NAME="C_OUTCLK_SUM_ROW4" VALUE="no_CLK_OUT4_output"/>
        <PARAMETER NAME="C_OUTCLK_SUM_ROW5" VALUE="no_CLK_OUT5_output"/>
        <PARAMETER NAME="C_OUTCLK_SUM_ROW6" VALUE="no_CLK_OUT6_output"/>
        <PARAMETER NAME="C_OUTCLK_SUM_ROW7" VALUE="no_CLK_OUT7_output"/>
        <PARAMETER NAME="C_CLKOUT1_REQUESTED_OUT_FREQ" VALUE="122.88"/>
        <PARAMETER NAME="C_CLKOUT2_REQUESTED_OUT_FREQ" VALUE="245.76"/>
        <PARAMETER NAME="C_CLKOUT3_REQUESTED_OUT_FREQ" VALUE="245.76"/>
        <PARAMETER NAME="C_CLKOUT4_REQUESTED_OUT_FREQ" VALUE="100.000"/>
        <PARAMETER NAME="C_CLKOUT5_REQUESTED_OUT_FREQ" VALUE="100.000"/>
        <PARAMETER NAME="C_CLKOUT6_REQUESTED_OUT_FREQ" VALUE="100.000"/>
        <PARAMETER NAME="C_CLKOUT7_REQUESTED_OUT_FREQ" VALUE="100.000"/>
        <PARAMETER NAME="C_CLKOUT1_REQUESTED_PHASE" VALUE="0.000"/>
        <PARAMETER NAME="C_CLKOUT2_REQUESTED_PHASE" VALUE="157.5"/>
        <PARAMETER NAME="C_CLKOUT3_REQUESTED_PHASE" VALUE="202.5"/>
        <PARAMETER NAME="C_CLKOUT4_REQUESTED_PHASE" VALUE="0.000"/>
        <PARAMETER NAME="C_CLKOUT5_REQUESTED_PHASE" VALUE="0.000"/>
        <PARAMETER NAME="C_CLKOUT6_REQUESTED_PHASE" VALUE="0.000"/>
        <PARAMETER NAME="C_CLKOUT7_REQUESTED_PHASE" VALUE="0.000"/>
        <PARAMETER NAME="C_CLKOUT1_REQUESTED_DUTY_CYCLE" VALUE="50.000"/>
        <PARAMETER NAME="C_CLKOUT2_REQUESTED_DUTY_CYCLE" VALUE="50.000"/>
        <PARAMETER NAME="C_CLKOUT3_REQUESTED_DUTY_CYCLE" VALUE="50.000"/>
        <PARAMETER NAME="C_CLKOUT4_REQUESTED_DUTY_CYCLE" VALUE="50.000"/>
        <PARAMETER NAME="C_CLKOUT5_REQUESTED_DUTY_CYCLE" VALUE="50.000"/>
        <PARAMETER NAME="C_CLKOUT6_REQUESTED_DUTY_CYCLE" VALUE="50.000"/>
        <PARAMETER NAME="C_CLKOUT7_REQUESTED_DUTY_CYCLE" VALUE="50.000"/>
        <PARAMETER NAME="C_CLKOUT1_OUT_FREQ" VALUE="122.88000"/>
        <PARAMETER NAME="C_CLKOUT2_OUT_FREQ" VALUE="245.76000"/>
        <PARAMETER NAME="C_CLKOUT3_OUT_FREQ" VALUE="245.76000"/>
        <PARAMETER NAME="C_CLKOUT4_OUT_FREQ" VALUE="100.000"/>
        <PARAMETER NAME="C_CLKOUT5_OUT_FREQ" VALUE="100.000"/>
        <PARAMETER NAME="C_CLKOUT6_OUT_FREQ" VALUE="100.000"/>
        <PARAMETER NAME="C_CLKOUT7_OUT_FREQ" VALUE="100.000"/>
        <PARAMETER NAME="C_CLKOUT1_PHASE" VALUE="0.000"/>
        <PARAMETER NAME="C_CLKOUT2_PHASE" VALUE="157.500"/>
        <PARAMETER NAME="C_CLKOUT3_PHASE" VALUE="202.500"/>
        <PARAMETER NAME="C_CLKOUT4_PHASE" VALUE="0.000"/>
        <PARAMETER NAME="C_CLKOUT5_PHASE" VALUE="0.000"/>
        <PARAMETER NAME="C_CLKOUT6_PHASE" VALUE="0.000"/>
        <PARAMETER NAME="C_CLKOUT7_PHASE" VALUE="0.000"/>
        <PARAMETER NAME="C_CLKOUT1_DUTY_CYCLE" VALUE="50.0"/>
        <PARAMETER NAME="C_CLKOUT2_DUTY_CYCLE" VALUE="50.0"/>
        <PARAMETER NAME="C_CLKOUT3_DUTY_CYCLE" VALUE="50.0"/>
        <PARAMETER NAME="C_CLKOUT4_DUTY_CYCLE" VALUE="50.000"/>
        <PARAMETER NAME="C_CLKOUT5_DUTY_CYCLE" VALUE="50.000"/>
        <PARAMETER NAME="C_CLKOUT6_DUTY_CYCLE" VALUE="50.000"/>
        <PARAMETER NAME="C_CLKOUT7_DUTY_CYCLE" VALUE="50.000"/>
        <PARAMETER NAME="C_USE_SAFE_CLOCK_STARTUP" VALUE="0"/>
        <PARAMETER NAME="C_USE_CLOCK_SEQUENCING" VALUE="0"/>
        <PARAMETER NAME="C_CLKOUT1_SEQUENCE_NUMBER" VALUE="1"/>
        <PARAMETER NAME="C_CLKOUT2_SEQUENCE_NUMBER" VALUE="1"/>
        <PARAMETER NAME="C_CLKOUT3_SEQUENCE_NUMBER" VALUE="1"/>
        <PARAMETER NAME="C_CLKOUT4_SEQUENCE_NUMBER" VALUE="1"/>
        <PARAMETER NAME="C_CLKOUT5_SEQUENCE_NUMBER" VALUE="1"/>
        <PARAMETER NAME="C_CLKOUT6_SEQUENCE_NUMBER" VALUE="1"/>
        <PARAMETER NAME="C_CLKOUT7_SEQUENCE_NUMBER" VALUE="1"/>
        <PARAMETER NAME="C_MMCM_NOTES" VALUE="None"/>
        <PARAMETER NAME="C_MMCM_BANDWIDTH" VALUE="OPTIMIZED"/>
        <PARAMETER NAME="C_MMCM_CLKFBOUT_MULT_F" VALUE="8.000"/>
        <PARAMETER NAME="C_MMCM_CLKIN1_PERIOD" VALUE="8.138"/>
        <PARAMETER NAME="C_MMCM_CLKIN2_PERIOD" VALUE="10.0"/>
        <PARAMETER NAME="C_MMCM_CLKOUT4_CASCADE" VALUE="FALSE"/>
        <PARAMETER NAME="C_MMCM_CLOCK_HOLD" VALUE="FALSE"/>
        <PARAMETER NAME="C_MMCM_COMPENSATION" VALUE="ZHOLD"/>
        <PARAMETER NAME="C_MMCM_DIVCLK_DIVIDE" VALUE="1"/>
        <PARAMETER NAME="C_MMCM_REF_JITTER1" VALUE="0.010"/>
        <PARAMETER NAME="C_MMCM_REF_JITTER2" VALUE="0.010"/>
        <PARAMETER NAME="C_MMCM_STARTUP_WAIT" VALUE="FALSE"/>
        <PARAMETER NAME="C_MMCM_CLKOUT0_DIVIDE_F" VALUE="8.000"/>
        <PARAMETER NAME="C_MMCM_CLKOUT1_DIVIDE" VALUE="4"/>
        <PARAMETER NAME="C_MMCM_CLKOUT2_DIVIDE" VALUE="4"/>
        <PARAMETER NAME="C_MMCM_CLKOUT3_DIVIDE" VALUE="1"/>
        <PARAMETER NAME="C_MMCM_CLKOUT4_DIVIDE" VALUE="1"/>
        <PARAMETER NAME="C_MMCM_CLKOUT5_DIVIDE" VALUE="1"/>
        <PARAMETER NAME="C_MMCM_CLKOUT6_DIVIDE" VALUE="1"/>
        <PARAMETER NAME="C_MMCM_CLKOUT0_DUTY_CYCLE" VALUE="0.500"/>
        <PARAMETER NAME="C_MMCM_CLKOUT1_DUTY_CYCLE" VALUE="0.500"/>
        <PARAMETER NAME="C_MMCM_CLKOUT2_DUTY_CYCLE" VALUE="0.500"/>
        <PARAMETER NAME="C_MMCM_CLKOUT3_DUTY_CYCLE" VALUE="0.500"/>
        <PARAMETER NAME="C_MMCM_CLKOUT4_DUTY_CYCLE" VALUE="0.500"/>
        <PARAMETER NAME="C_MMCM_CLKOUT5_DUTY_CYCLE" VALUE="0.500"/>
        <PARAMETER NAME="C_MMCM_CLKOUT6_DUTY_CYCLE" VALUE="0.500"/>
        <PARAMETER NAME="C_MMCM_CLKFBOUT_PHASE" VALUE="0.000"/>
        <PARAMETER NAME="C_MMCM_CLKOUT0_PHASE" VALUE="0.000"/>
        <PARAMETER NAME="C_MMCM_CLKOUT1_PHASE" VALUE="157.500"/>
        <PARAMETER NAME="C_MMCM_CLKOUT2_PHASE" VALUE="202.500"/>
        <PARAMETER NAME="C_MMCM_CLKOUT3_PHASE" VALUE="0.000"/>
        <PARAMETER NAME="C_MMCM_CLKOUT4_PHASE" VALUE="0.000"/>
        <PARAMETER NAME="C_MMCM_CLKOUT5_PHASE" VALUE="0.000"/>
        <PARAMETER NAME="C_MMCM_CLKOUT6_PHASE" VALUE="0.000"/>
        <PARAMETER NAME="C_MMCM_CLKFBOUT_USE_FINE_PS" VALUE="FALSE"/>
        <PARAMETER NAME="C_MMCM_CLKOUT0_USE_FINE_PS" VALUE="FALSE"/>
        <PARAMETER NAME="C_MMCM_CLKOUT1_USE_FINE_PS" VALUE="FALSE"/>
        <PARAMETER NAME="C_MMCM_CLKOUT2_USE_FINE_PS" VALUE="FALSE"/>
        <PARAMETER NAME="C_MMCM_CLKOUT3_USE_FINE_PS" VALUE="FALSE"/>
        <PARAMETER NAME="C_MMCM_CLKOUT4_USE_FINE_PS" VALUE="FALSE"/>
        <PARAMETER NAME="C_MMCM_CLKOUT5_USE_FINE_PS" VALUE="FALSE"/>
        <PARAMETER NAME="C_MMCM_CLKOUT6_USE_FINE_PS" VALUE="FALSE"/>
        <PARAMETER NAME="C_PLL_NOTES" VALUE="No notes"/>
        <PARAMETER NAME="C_PLL_BANDWIDTH" VALUE="OPTIMIZED"/>
        <PARAMETER NAME="C_PLL_CLK_FEEDBACK" VALUE="CLKFBOUT"/>
        <PARAMETER NAME="C_PLL_CLKFBOUT_MULT" VALUE="1"/>
        <PARAMETER NAME="C_PLL_CLKIN_PERIOD" VALUE="1.000"/>
        <PARAMETER NAME="C_PLL_COMPENSATION" VALUE="SYSTEM_SYNCHRONOUS"/>
        <PARAMETER NAME="C_PLL_DIVCLK_DIVIDE" VALUE="1"/>
        <PARAMETER NAME="C_PLL_REF_JITTER" VALUE="0.010"/>
        <PARAMETER NAME="C_PLL_CLKOUT0_DIVIDE" VALUE="1"/>
        <PARAMETER NAME="C_PLL_CLKOUT1_DIVIDE" VALUE="1"/>
        <PARAMETER NAME="C_PLL_CLKOUT2_DIVIDE" VALUE="1"/>
        <PARAMETER NAME="C_PLL_CLKOUT3_DIVIDE" VALUE="1"/>
        <PARAMETER NAME="C_PLL_CLKOUT4_DIVIDE" VALUE="1"/>
        <PARAMETER NAME="C_PLL_CLKOUT5_DIVIDE" VALUE="1"/>
        <PARAMETER NAME="C_PLL_CLKOUT0_DUTY_CYCLE" VALUE="0.500"/>
        <PARAMETER NAME="C_PLL_CLKOUT1_DUTY_CYCLE" VALUE="0.500"/>
        <PARAMETER NAME="C_PLL_CLKOUT2_DUTY_CYCLE" VALUE="0.500"/>
        <PARAMETER NAME="C_PLL_CLKOUT3_DUTY_CYCLE" VALUE="0.500"/>
        <PARAMETER NAME="C_PLL_CLKOUT4_DUTY_CYCLE" VALUE="0.500"/>
        <PARAMETER NAME="C_PLL_CLKOUT5_DUTY_CYCLE" VALUE="0.500"/>
        <PARAMETER NAME="C_PLL_CLKFBOUT_PHASE" VALUE="0.000"/>
        <PARAMETER NAME="C_PLL_CLKOUT0_PHASE" VALUE="0.000"/>
        <PARAMETER NAME="C_PLL_CLKOUT1_PHASE" VALUE="0.000"/>
        <PARAMETER NAME="C_PLL_CLKOUT2_PHASE" VALUE="0.000"/>
        <PARAMETER NAME="C_PLL_CLKOUT3_PHASE" VALUE="0.000"/>
        <PARAMETER NAME="C_PLL_CLKOUT4_PHASE" VALUE="0.000"/>
        <PARAMETER NAME="C_PLL_CLKOUT5_PHASE" VALUE="0.000"/>
        <PARAMETER NAME="C_CLOCK_MGR_TYPE" VALUE="NA"/>
        <PARAMETER NAME="C_OVERRIDE_MMCM" VALUE="0"/>
        <PARAMETER NAME="C_OVERRIDE_PLL" VALUE="0"/>
        <PARAMETER NAME="C_PRIMARY_PORT" VALUE="clk_in1"/>
        <PARAMETER NAME="C_SECONDARY_PORT" VALUE="clk_in2"/>
        <PARAMETER NAME="C_CLK_OUT1_PORT" VALUE="clk_out1"/>
        <PARAMETER NAME="C_CLK_OUT2_PORT" VALUE="clk_out2"/>
        <PARAMETER NAME="C_CLK_OUT3_PORT" VALUE="clk_out3"/>
        <PARAMETER NAME="C_CLK_OUT4_PORT" VALUE="clk_out4"/>
        <PARAMETER NAME="C_CLK_OUT5_PORT" VALUE="clk_out5"/>
        <PARAMETER NAME="C_CLK_OUT6_PORT" VALUE="clk_out6"/>
        <PARAMETER NAME="C_CLK_OUT7_PORT" VALUE="clk_out7"/>
        <PARAMETER NAME="C_RESET_PORT" VALUE="reset"/>
        <PARAMETER NAME="C_LOCKED_PORT" VALUE="locked"/>
        <PARAMETER NAME="C_CLKFB_IN_PORT" VALUE="clkfb_in"/>
        <PARAMETER NAME="C_CLKFB_IN_P_PORT" VALUE="clkfb_in_p"/>
        <PARAMETER NAME="C_CLKFB_IN_N_PORT" VALUE="clkfb_in_n"/>
        <PARAMETER NAME="C_CLKFB_OUT_PORT" VALUE="clkfb_out"/>
        <PARAMETER NAME="C_CLKFB_OUT_P_PORT" VALUE="clkfb_out_p"/>
        <PARAMETER NAME="C_CLKFB_OUT_N_PORT" VALUE="clkfb_out_n"/>
        <PARAMETER NAME="C_POWER_DOWN_PORT" VALUE="power_down"/>
        <PARAMETER NAME="C_DADDR_PORT" VALUE="daddr"/>
        <PARAMETER NAME="C_DCLK_PORT" VALUE="dclk"/>
        <PARAMETER NAME="C_DRDY_PORT" VALUE="drdy"/>
        <PARAMETER NAME="C_DWE_PORT" VALUE="dwe"/>
        <PARAMETER NAME="C_DIN_PORT" VALUE="din"/>
        <PARAMETER NAME="C_DOUT_PORT" VALUE="dout"/>
        <PARAMETER NAME="C_DEN_PORT" VALUE="den"/>
        <PARAMETER NAME="C_PSCLK_PORT" VALUE="psclk"/>
        <PARAMETER NAME="C_PSEN_PORT" VALUE="psen"/>
        <PARAMETER NAME="C_PSINCDEC_PORT" VALUE="psincdec"/>
        <PARAMETER NAME="C_PSDONE_PORT" VALUE="psdone"/>
        <PARAMETER NAME="C_CLK_VALID_PORT" VALUE="CLK_VALID"/>
        <PARAMETER NAME="C_STATUS_PORT" VALUE="STATUS"/>
        <PARAMETER NAME="C_CLK_IN_SEL_PORT" VALUE="clk_in_sel"/>
        <PARAMETER NAME="C_INPUT_CLK_STOPPED_PORT" VALUE="input_clk_stopped"/>
        <PARAMETER NAME="C_CLKFB_STOPPED_PORT" VALUE="clkfb_stopped"/>
        <PARAMETER NAME="C_CLKIN1_JITTER_PS" VALUE="81.38"/>
        <PARAMETER NAME="C_CLKIN2_JITTER_PS" VALUE="100.0"/>
        <PARAMETER NAME="C_PRIMITIVE" VALUE="PLL"/>
        <PARAMETER NAME="C_SS_MODE" VALUE="CENTER_HIGH"/>
        <PARAMETER NAME="C_SS_MOD_PERIOD" VALUE="4000"/>
        <PARAMETER NAME="C_SS_MOD_TIME" VALUE="0.004"/>
        <PARAMETER NAME="C_HAS_CDDC" VALUE="0"/>
        <PARAMETER NAME="C_CDDCDONE_PORT" VALUE="cddcdone"/>
        <PARAMETER NAME="C_CDDCREQ_PORT" VALUE="cddcreq"/>
        <PARAMETER NAME="C_CLKOUTPHY_MODE" VALUE="VCO"/>
        <PARAMETER NAME="C_ENABLE_CLKOUTPHY" VALUE="0"/>
        <PARAMETER NAME="C_INTERFACE_SELECTION" VALUE="0"/>
        <PARAMETER NAME="C_S_AXI_ADDR_WIDTH" VALUE="11"/>
        <PARAMETER NAME="C_S_AXI_DATA_WIDTH" VALUE="32"/>
        <PARAMETER NAME="C_POWER_REG" VALUE="0000"/>
        <PARAMETER NAME="C_CLKOUT0_1" VALUE="0000"/>
        <PARAMETER NAME="C_CLKOUT0_2" VALUE="0000"/>
        <PARAMETER NAME="C_CLKOUT1_1" VALUE="0000"/>
        <PARAMETER NAME="C_CLKOUT1_2" VALUE="0000"/>
        <PARAMETER NAME="C_CLKOUT2_1" VALUE="0000"/>
        <PARAMETER NAME="C_CLKOUT2_2" VALUE="0000"/>
        <PARAMETER NAME="C_CLKOUT3_1" VALUE="0000"/>
        <PARAMETER NAME="C_CLKOUT3_2" VALUE="0000"/>
        <PARAMETER NAME="C_CLKOUT4_1" VALUE="0000"/>
        <PARAMETER NAME="C_CLKOUT4_2" VALUE="0000"/>
        <PARAMETER NAME="C_CLKOUT5_1" VALUE="0000"/>
        <PARAMETER NAME="C_CLKOUT5_2" VALUE="0000"/>
        <PARAMETER NAME="C_CLKOUT6_1" VALUE="0000"/>
        <PARAMETER NAME="C_CLKOUT6_2" VALUE="0000"/>
        <PARAMETER NAME="C_CLKFBOUT_1" VALUE="0000"/>
        <PARAMETER NAME="C_CLKFBOUT_2" VALUE="0000"/>
        <PARAMETER NAME="C_DIVCLK" VALUE="0000"/>
        <PARAMETER NAME="C_LOCK_1" VALUE="0000"/>
        <PARAMETER NAME="C_LOCK_2" VALUE="0000"/>
        <PARAMETER NAME="C_LOCK_3" VALUE="0000"/>
        <PARAMETER NAME="C_FILTER_1" VALUE="0000"/>
        <PARAMETER NAME="C_FILTER_2" VALUE="0000"/>
        <PARAMETER NAME="C_DIVIDE1_AUTO" VALUE="1"/>
        <PARAMETER NAME="C_DIVIDE2_AUTO" VALUE="0.5"/>
        <PARAMETER NAME="C_DIVIDE3_AUTO" VALUE="0.5"/>
        <PARAMETER NAME="C_DIVIDE4_AUTO" VALUE="0.125"/>
        <PARAMETER NAME="C_DIVIDE5_AUTO" VALUE="0.125"/>
        <PARAMETER NAME="C_DIVIDE6_AUTO" VALUE="0.125"/>
        <PARAMETER NAME="C_DIVIDE7_AUTO" VALUE="0.125"/>
        <PARAMETER NAME="C_PLLBUFGCEDIV" VALUE="false"/>
        <PARAMETER NAME="C_MMCMBUFGCEDIV" VALUE="false"/>
        <PARAMETER NAME="C_PLLBUFGCEDIV1" VALUE="false"/>
        <PARAMETER NAME="C_PLLBUFGCEDIV2" VALUE="false"/>
        <PARAMETER NAME="C_PLLBUFGCEDIV3" VALUE="false"/>
        <PARAMETER NAME="C_PLLBUFGCEDIV4" VALUE="false"/>
        <PARAMETER NAME="C_MMCMBUFGCEDIV1" VALUE="false"/>
        <PARAMETER NAME="C_MMCMBUFGCEDIV2" VALUE="false"/>
        <PARAMETER NAME="C_MMCMBUFGCEDIV3" VALUE="false"/>
        <PARAMETER NAME="C_MMCMBUFGCEDIV4" VALUE="false"/>
        <PARAMETER NAME="C_MMCMBUFGCEDIV5" VALUE="false"/>
        <PARAMETER NAME="C_MMCMBUFGCEDIV6" VALUE="false"/>
        <PARAMETER NAME="C_MMCMBUFGCEDIV7" VALUE="false"/>
        <PARAMETER NAME="C_CLKOUT1_MATCHED_ROUTING" VALUE="false"/>
        <PARAMETER NAME="C_CLKOUT2_MATCHED_ROUTING" VALUE="false"/>
        <PARAMETER NAME="C_CLKOUT3_MATCHED_ROUTING" VALUE="false"/>
        <PARAMETER NAME="C_CLKOUT4_MATCHED_ROUTING" VALUE="false"/>
        <PARAMETER NAME="C_CLKOUT5_MATCHED_ROUTING" VALUE="false"/>
        <PARAMETER NAME="C_CLKOUT6_MATCHED_ROUTING" VALUE="false"/>
        <PARAMETER NAME="C_CLKOUT7_MATCHED_ROUTING" VALUE="false"/>
        <PARAMETER NAME="C_CLKOUT0_ACTUAL_FREQ" VALUE="122.88000"/>
        <PARAMETER NAME="C_CLKOUT1_ACTUAL_FREQ" VALUE="245.76000"/>
        <PARAMETER NAME="C_CLKOUT2_ACTUAL_FREQ" VALUE="245.76000"/>
        <PARAMETER NAME="C_CLKOUT3_ACTUAL_FREQ" VALUE="100.000"/>
        <PARAMETER NAME="C_CLKOUT4_ACTUAL_FREQ" VALUE="100.000"/>
        <PARAMETER NAME="C_CLKOUT5_ACTUAL_FREQ" VALUE="100.000"/>
        <PARAMETER NAME="C_CLKOUT6_ACTUAL_FREQ" VALUE="100.000"/>
        <PARAMETER NAME="C_M_MAX" VALUE="64.000"/>
        <PARAMETER NAME="C_M_MIN" VALUE="2.000"/>
        <PARAMETER NAME="C_D_MAX" VALUE="42.000"/>
        <PARAMETER NAME="C_D_MIN" VALUE="1.000"/>
        <PARAMETER NAME="C_O_MAX" VALUE="128.000"/>
        <PARAMETER NAME="C_O_MIN" VALUE="1.000"/>
        <PARAMETER NAME="C_VCO_MIN" VALUE="800.000"/>
        <PARAMETER NAME="C_VCO_MAX" VALUE="1600.000"/>
        <PARAMETER NAME="Component_Name" VALUE="system_pll_0_0"/>
        <PARAMETER NAME="USER_CLK_FREQ0" VALUE="100.0"/>
        <PARAMETER NAME="USER_CLK_FREQ1" VALUE="100.0"/>
        <PARAMETER NAME="USER_CLK_FREQ2" VALUE="100.0"/>
        <PARAMETER NAME="USER_CLK_FREQ3" VALUE="100.0"/>
        <PARAMETER NAME="ENABLE_CLOCK_MONITOR" VALUE="false"/>
        <PARAMETER NAME="OPTIMIZE_CLOCKING_STRUCTURE_EN" VALUE="false"/>
        <PARAMETER NAME="ENABLE_USER_CLOCK0" VALUE="false"/>
        <PARAMETER NAME="ENABLE_USER_CLOCK1" VALUE="false"/>
        <PARAMETER NAME="ENABLE_USER_CLOCK2" VALUE="false"/>
        <PARAMETER NAME="ENABLE_USER_CLOCK3" VALUE="false"/>
        <PARAMETER NAME="Enable_PLL0" VALUE="false"/>
        <PARAMETER NAME="Enable_PLL1" VALUE="false"/>
        <PARAMETER NAME="REF_CLK_FREQ" VALUE="100.0"/>
        <PARAMETER NAME="PRECISION" VALUE="1"/>
        <PARAMETER NAME="PRIMITIVE" VALUE="PLL"/>
        <PARAMETER NAME="PRIMTYPE_SEL" VALUE="mmcm_adv"/>
        <PARAMETER NAME="CLOCK_MGR_TYPE" VALUE="auto"/>
        <PARAMETER NAME="USE_FREQ_SYNTH" VALUE="true"/>
        <PARAMETER NAME="USE_SPREAD_SPECTRUM" VALUE="false"/>
        <PARAMETER NAME="USE_PHASE_ALIGNMENT" VALUE="true"/>
        <PARAMETER NAME="USE_MIN_POWER" VALUE="false"/>
        <PARAMETER NAME="USE_DYN_PHASE_SHIFT" VALUE="false"/>
        <PARAMETER NAME="USE_DYN_RECONFIG" VALUE="false"/>
        <PARAMETER NAME="JITTER_SEL" VALUE="No_Jitter"/>
        <PARAMETER NAME="PRIM_IN_FREQ" VALUE="122.88"/>
        <PARAMETER NAME="PRIM_IN_TIMEPERIOD" VALUE="10.000"/>
        <PARAMETER NAME="IN_FREQ_UNITS" VALUE="Units_MHz"/>
        <PARAMETER NAME="PHASESHIFT_MODE" VALUE="WAVEFORM"/>
        <PARAMETER NAME="IN_JITTER_UNITS" VALUE="Units_UI"/>
        <PARAMETER NAME="RELATIVE_INCLK" VALUE="REL_PRIMARY"/>
        <PARAMETER NAME="USE_INCLK_SWITCHOVER" VALUE="false"/>
        <PARAMETER NAME="SECONDARY_IN_FREQ" VALUE="100.000"/>
        <PARAMETER NAME="SECONDARY_IN_TIMEPERIOD" VALUE="10.000"/>
        <PARAMETER NAME="SECONDARY_PORT" VALUE="clk_in2"/>
        <PARAMETER NAME="SECONDARY_SOURCE" VALUE="Single_ended_clock_capable_pin"/>
        <PARAMETER NAME="JITTER_OPTIONS" VALUE="UI"/>
        <PARAMETER NAME="CLKIN1_UI_JITTER" VALUE="0.010"/>
        <PARAMETER NAME="CLKIN2_UI_JITTER" VALUE="0.010"/>
        <PARAMETER NAME="PRIM_IN_JITTER" VALUE="0.010"/>
        <PARAMETER NAME="SECONDARY_IN_JITTER" VALUE="0.010"/>
        <PARAMETER NAME="CLKIN1_JITTER_PS" VALUE="81.38"/>
        <PARAMETER NAME="CLKIN2_JITTER_PS" VALUE="100.0"/>
        <PARAMETER NAME="CLKOUT1_USED" VALUE="true"/>
        <PARAMETER NAME="CLKOUT2_USED" VALUE="true"/>
        <PARAMETER NAME="CLKOUT3_USED" VALUE="true"/>
        <PARAMETER NAME="CLKOUT4_USED" VALUE="false"/>
        <PARAMETER NAME="CLKOUT5_USED" VALUE="false"/>
        <PARAMETER NAME="CLKOUT6_USED" VALUE="false"/>
        <PARAMETER NAME="CLKOUT7_USED" VALUE="false"/>
        <PARAMETER NAME="NUM_OUT_CLKS" VALUE="3"/>
        <PARAMETER NAME="CLK_OUT1_USE_FINE_PS_GUI" VALUE="false"/>
        <PARAMETER NAME="CLK_OUT2_USE_FINE_PS_GUI" VALUE="false"/>
        <PARAMETER NAME="CLK_OUT3_USE_FINE_PS_GUI" VALUE="false"/>
        <PARAMETER NAME="CLK_OUT4_USE_FINE_PS_GUI" VALUE="false"/>
        <PARAMETER NAME="CLK_OUT5_USE_FINE_PS_GUI" VALUE="false"/>
        <PARAMETER NAME="CLK_OUT6_USE_FINE_PS_GUI" VALUE="false"/>
        <PARAMETER NAME="CLK_OUT7_USE_FINE_PS_GUI" VALUE="false"/>
        <PARAMETER NAME="PRIMARY_PORT" VALUE="clk_in1"/>
        <PARAMETER NAME="CLK_OUT1_PORT" VALUE="clk_out1"/>
        <PARAMETER NAME="CLK_OUT2_PORT" VALUE="clk_out2"/>
        <PARAMETER NAME="CLK_OUT3_PORT" VALUE="clk_out3"/>
        <PARAMETER NAME="CLK_OUT4_PORT" VALUE="clk_out4"/>
        <PARAMETER NAME="CLK_OUT5_PORT" VALUE="clk_out5"/>
        <PARAMETER NAME="CLK_OUT6_PORT" VALUE="clk_out6"/>
        <PARAMETER NAME="CLK_OUT7_PORT" VALUE="clk_out7"/>
        <PARAMETER NAME="DADDR_PORT" VALUE="daddr"/>
        <PARAMETER NAME="DCLK_PORT" VALUE="dclk"/>
        <PARAMETER NAME="DRDY_PORT" VALUE="drdy"/>
        <PARAMETER NAME="DWE_PORT" VALUE="dwe"/>
        <PARAMETER NAME="DIN_PORT" VALUE="din"/>
        <PARAMETER NAME="DOUT_PORT" VALUE="dout"/>
        <PARAMETER NAME="DEN_PORT" VALUE="den"/>
        <PARAMETER NAME="PSCLK_PORT" VALUE="psclk"/>
        <PARAMETER NAME="PSEN_PORT" VALUE="psen"/>
        <PARAMETER NAME="PSINCDEC_PORT" VALUE="psincdec"/>
        <PARAMETER NAME="PSDONE_PORT" VALUE="psdone"/>
        <PARAMETER NAME="CLKOUT1_REQUESTED_OUT_FREQ" VALUE="122.88"/>
        <PARAMETER NAME="CLKOUT1_REQUESTED_PHASE" VALUE="0.000"/>
        <PARAMETER NAME="CLKOUT1_REQUESTED_DUTY_CYCLE" VALUE="50.000"/>
        <PARAMETER NAME="CLKOUT2_REQUESTED_OUT_FREQ" VALUE="245.76"/>
        <PARAMETER NAME="CLKOUT2_REQUESTED_PHASE" VALUE="157.5"/>
        <PARAMETER NAME="CLKOUT2_REQUESTED_DUTY_CYCLE" VALUE="50.000"/>
        <PARAMETER NAME="CLKOUT3_REQUESTED_OUT_FREQ" VALUE="245.76"/>
        <PARAMETER NAME="CLKOUT3_REQUESTED_PHASE" VALUE="202.5"/>
        <PARAMETER NAME="CLKOUT3_REQUESTED_DUTY_CYCLE" VALUE="50.000"/>
        <PARAMETER NAME="CLKOUT4_REQUESTED_OUT_FREQ" VALUE="100.000"/>
        <PARAMETER NAME="CLKOUT4_REQUESTED_PHASE" VALUE="0.000"/>
        <PARAMETER NAME="CLKOUT4_REQUESTED_DUTY_CYCLE" VALUE="50.000"/>
        <PARAMETER NAME="CLKOUT5_REQUESTED_OUT_FREQ" VALUE="100.000"/>
        <PARAMETER NAME="CLKOUT5_REQUESTED_PHASE" VALUE="0.000"/>
        <PARAMETER NAME="CLKOUT5_REQUESTED_DUTY_CYCLE" VALUE="50.000"/>
        <PARAMETER NAME="CLKOUT6_REQUESTED_OUT_FREQ" VALUE="100.000"/>
        <PARAMETER NAME="CLKOUT6_REQUESTED_PHASE" VALUE="0.000"/>
        <PARAMETER NAME="CLKOUT6_REQUESTED_DUTY_CYCLE" VALUE="50.000"/>
        <PARAMETER NAME="CLKOUT7_REQUESTED_OUT_FREQ" VALUE="100.000"/>
        <PARAMETER NAME="CLKOUT7_REQUESTED_PHASE" VALUE="0.000"/>
        <PARAMETER NAME="CLKOUT7_REQUESTED_DUTY_CYCLE" VALUE="50.000"/>
        <PARAMETER NAME="USE_MAX_I_JITTER" VALUE="false"/>
        <PARAMETER NAME="USE_MIN_O_JITTER" VALUE="false"/>
        <PARAMETER NAME="CLKOUT1_MATCHED_ROUTING" VALUE="false"/>
        <PARAMETER NAME="CLKOUT2_MATCHED_ROUTING" VALUE="false"/>
        <PARAMETER NAME="CLKOUT3_MATCHED_ROUTING" VALUE="false"/>
        <PARAMETER NAME="CLKOUT4_MATCHED_ROUTING" VALUE="false"/>
        <PARAMETER NAME="CLKOUT5_MATCHED_ROUTING" VALUE="false"/>
        <PARAMETER NAME="CLKOUT6_MATCHED_ROUTING" VALUE="false"/>
        <PARAMETER NAME="CLKOUT7_MATCHED_ROUTING" VALUE="false"/>
        <PARAMETER NAME="PRIM_SOURCE" VALUE="Differential_clock_capable_pin"/>
        <PARAMETER NAME="CLKOUT1_DRIVES" VALUE="BUFG"/>
        <PARAMETER NAME="CLKOUT2_DRIVES" VALUE="BUFG"/>
        <PARAMETER NAME="CLKOUT3_DRIVES" VALUE="BUFG"/>
        <PARAMETER NAME="CLKOUT4_DRIVES" VALUE="BUFG"/>
        <PARAMETER NAME="CLKOUT5_DRIVES" VALUE="BUFG"/>
        <PARAMETER NAME="CLKOUT6_DRIVES" VALUE="BUFG"/>
        <PARAMETER NAME="CLKOUT7_DRIVES" VALUE="BUFG"/>
        <PARAMETER NAME="FEEDBACK_SOURCE" VALUE="FDBK_AUTO"/>
        <PARAMETER NAME="CLKFB_IN_SIGNALING" VALUE="SINGLE"/>
        <PARAMETER NAME="CLKFB_IN_PORT" VALUE="clkfb_in"/>
        <PARAMETER NAME="CLKFB_IN_P_PORT" VALUE="clkfb_in_p"/>
        <PARAMETER NAME="CLKFB_IN_N_PORT" VALUE="clkfb_in_n"/>
        <PARAMETER NAME="CLKFB_OUT_PORT" VALUE="clkfb_out"/>
        <PARAMETER NAME="CLKFB_OUT_P_PORT" VALUE="clkfb_out_p"/>
        <PARAMETER NAME="CLKFB_OUT_N_PORT" VALUE="clkfb_out_n"/>
        <PARAMETER NAME="PLATFORM" VALUE="UNKNOWN"/>
        <PARAMETER NAME="SUMMARY_STRINGS" VALUE="empty"/>
        <PARAMETER NAME="USE_LOCKED" VALUE="true"/>
        <PARAMETER NAME="CALC_DONE" VALUE="empty"/>
        <PARAMETER NAME="USE_RESET" VALUE="false"/>
        <PARAMETER NAME="USE_POWER_DOWN" VALUE="false"/>
        <PARAMETER NAME="USE_STATUS" VALUE="false"/>
        <PARAMETER NAME="USE_FREEZE" VALUE="false"/>
        <PARAMETER NAME="USE_CLK_VALID" VALUE="false"/>
        <PARAMETER NAME="USE_INCLK_STOPPED" VALUE="false"/>
        <PARAMETER NAME="USE_CLKFB_STOPPED" VALUE="false"/>
        <PARAMETER NAME="RESET_PORT" VALUE="reset"/>
        <PARAMETER NAME="LOCKED_PORT" VALUE="locked"/>
        <PARAMETER NAME="POWER_DOWN_PORT" VALUE="power_down"/>
        <PARAMETER NAME="CLK_VALID_PORT" VALUE="CLK_VALID"/>
        <PARAMETER NAME="STATUS_PORT" VALUE="STATUS"/>
        <PARAMETER NAME="CLK_IN_SEL_PORT" VALUE="clk_in_sel"/>
        <PARAMETER NAME="INPUT_CLK_STOPPED_PORT" VALUE="input_clk_stopped"/>
        <PARAMETER NAME="CLKFB_STOPPED_PORT" VALUE="clkfb_stopped"/>
        <PARAMETER NAME="SS_MODE" VALUE="CENTER_HIGH"/>
        <PARAMETER NAME="SS_MOD_FREQ" VALUE="250"/>
        <PARAMETER NAME="SS_MOD_TIME" VALUE="0.004"/>
        <PARAMETER NAME="OVERRIDE_MMCM" VALUE="false"/>
        <PARAMETER NAME="MMCM_NOTES" VALUE="None"/>
        <PARAMETER NAME="MMCM_DIVCLK_DIVIDE" VALUE="1"/>
        <PARAMETER NAME="MMCM_BANDWIDTH" VALUE="OPTIMIZED"/>
        <PARAMETER NAME="MMCM_CLKFBOUT_MULT_F" VALUE="8"/>
        <PARAMETER NAME="MMCM_CLKFBOUT_PHASE" VALUE="0.000"/>
        <PARAMETER NAME="MMCM_CLKFBOUT_USE_FINE_PS" VALUE="false"/>
        <PARAMETER NAME="MMCM_CLKIN1_PERIOD" VALUE="8.138"/>
        <PARAMETER NAME="MMCM_CLKIN2_PERIOD" VALUE="10.0"/>
        <PARAMETER NAME="MMCM_CLKOUT4_CASCADE" VALUE="false"/>
        <PARAMETER NAME="MMCM_CLOCK_HOLD" VALUE="false"/>
        <PARAMETER NAME="MMCM_COMPENSATION" VALUE="ZHOLD"/>
        <PARAMETER NAME="MMCM_REF_JITTER1" VALUE="0.010"/>
        <PARAMETER NAME="MMCM_REF_JITTER2" VALUE="0.010"/>
        <PARAMETER NAME="MMCM_STARTUP_WAIT" VALUE="false"/>
        <PARAMETER NAME="MMCM_CLKOUT0_DIVIDE_F" VALUE="8"/>
        <PARAMETER NAME="MMCM_CLKOUT0_DUTY_CYCLE" VALUE="0.500"/>
        <PARAMETER NAME="MMCM_CLKOUT0_PHASE" VALUE="0.000"/>
        <PARAMETER NAME="MMCM_CLKOUT0_USE_FINE_PS" VALUE="false"/>
        <PARAMETER NAME="MMCM_CLKOUT1_DIVIDE" VALUE="4"/>
        <PARAMETER NAME="MMCM_CLKOUT1_DUTY_CYCLE" VALUE="0.500"/>
        <PARAMETER NAME="MMCM_CLKOUT1_PHASE" VALUE="157.500"/>
        <PARAMETER NAME="MMCM_CLKOUT1_USE_FINE_PS" VALUE="false"/>
        <PARAMETER NAME="MMCM_CLKOUT2_DIVIDE" VALUE="4"/>
        <PARAMETER NAME="MMCM_CLKOUT2_DUTY_CYCLE" VALUE="0.500"/>
        <PARAMETER NAME="MMCM_CLKOUT2_PHASE" VALUE="202.500"/>
        <PARAMETER NAME="MMCM_CLKOUT2_USE_FINE_PS" VALUE="false"/>
        <PARAMETER NAME="MMCM_CLKOUT3_DIVIDE" VALUE="1"/>
        <PARAMETER NAME="MMCM_CLKOUT3_DUTY_CYCLE" VALUE="0.500"/>
        <PARAMETER NAME="MMCM_CLKOUT3_PHASE" VALUE="0.000"/>
        <PARAMETER NAME="MMCM_CLKOUT3_USE_FINE_PS" VALUE="false"/>
        <PARAMETER NAME="MMCM_CLKOUT4_DIVIDE" VALUE="1"/>
        <PARAMETER NAME="MMCM_CLKOUT4_DUTY_CYCLE" VALUE="0.500"/>
        <PARAMETER NAME="MMCM_CLKOUT4_PHASE" VALUE="0.000"/>
        <PARAMETER NAME="MMCM_CLKOUT4_USE_FINE_PS" VALUE="false"/>
        <PARAMETER NAME="MMCM_CLKOUT5_DIVIDE" VALUE="1"/>
        <PARAMETER NAME="MMCM_CLKOUT5_DUTY_CYCLE" VALUE="0.500"/>
        <PARAMETER NAME="MMCM_CLKOUT5_PHASE" VALUE="0.000"/>
        <PARAMETER NAME="MMCM_CLKOUT5_USE_FINE_PS" VALUE="false"/>
        <PARAMETER NAME="MMCM_CLKOUT6_DIVIDE" VALUE="1"/>
        <PARAMETER NAME="MMCM_CLKOUT6_DUTY_CYCLE" VALUE="0.500"/>
        <PARAMETER NAME="MMCM_CLKOUT6_PHASE" VALUE="0.000"/>
        <PARAMETER NAME="MMCM_CLKOUT6_USE_FINE_PS" VALUE="false"/>
        <PARAMETER NAME="OVERRIDE_PLL" VALUE="false"/>
        <PARAMETER NAME="PLL_NOTES" VALUE="None"/>
        <PARAMETER NAME="PLL_BANDWIDTH" VALUE="OPTIMIZED"/>
        <PARAMETER NAME="PLL_CLKFBOUT_MULT" VALUE="4"/>
        <PARAMETER NAME="PLL_CLKFBOUT_PHASE" VALUE="0.000"/>
        <PARAMETER NAME="PLL_CLK_FEEDBACK" VALUE="CLKFBOUT"/>
        <PARAMETER NAME="PLL_DIVCLK_DIVIDE" VALUE="1"/>
        <PARAMETER NAME="PLL_CLKIN_PERIOD" VALUE="8.138"/>
        <PARAMETER NAME="PLL_COMPENSATION" VALUE="SYSTEM_SYNCHRONOUS"/>
        <PARAMETER NAME="PLL_REF_JITTER" VALUE="0.010"/>
        <PARAMETER NAME="PLL_CLKOUT0_DIVIDE" VALUE="1"/>
        <PARAMETER NAME="PLL_CLKOUT0_DUTY_CYCLE" VALUE="0.500"/>
        <PARAMETER NAME="PLL_CLKOUT0_PHASE" VALUE="0.000"/>
        <PARAMETER NAME="PLL_CLKOUT1_DIVIDE" VALUE="1"/>
        <PARAMETER NAME="PLL_CLKOUT1_DUTY_CYCLE" VALUE="0.500"/>
        <PARAMETER NAME="PLL_CLKOUT1_PHASE" VALUE="0.000"/>
        <PARAMETER NAME="PLL_CLKOUT2_DIVIDE" VALUE="1"/>
        <PARAMETER NAME="PLL_CLKOUT2_DUTY_CYCLE" VALUE="0.500"/>
        <PARAMETER NAME="PLL_CLKOUT2_PHASE" VALUE="0.000"/>
        <PARAMETER NAME="PLL_CLKOUT3_DIVIDE" VALUE="1"/>
        <PARAMETER NAME="PLL_CLKOUT3_DUTY_CYCLE" VALUE="0.500"/>
        <PARAMETER NAME="PLL_CLKOUT3_PHASE" VALUE="0.000"/>
        <PARAMETER NAME="PLL_CLKOUT4_DIVIDE" VALUE="1"/>
        <PARAMETER NAME="PLL_CLKOUT4_DUTY_CYCLE" VALUE="0.500"/>
        <PARAMETER NAME="PLL_CLKOUT4_PHASE" VALUE="0.000"/>
        <PARAMETER NAME="PLL_CLKOUT5_DIVIDE" VALUE="1"/>
        <PARAMETER NAME="PLL_CLKOUT5_DUTY_CYCLE" VALUE="0.500"/>
        <PARAMETER NAME="PLL_CLKOUT5_PHASE" VALUE="0.000"/>
        <PARAMETER NAME="RESET_TYPE" VALUE="ACTIVE_HIGH"/>
        <PARAMETER NAME="USE_SAFE_CLOCK_STARTUP" VALUE="false"/>
        <PARAMETER NAME="USE_CLOCK_SEQUENCING" VALUE="false"/>
        <PARAMETER NAME="CLKOUT1_SEQUENCE_NUMBER" VALUE="1"/>
        <PARAMETER NAME="CLKOUT2_SEQUENCE_NUMBER" VALUE="1"/>
        <PARAMETER NAME="CLKOUT3_SEQUENCE_NUMBER" VALUE="1"/>
        <PARAMETER NAME="CLKOUT4_SEQUENCE_NUMBER" VALUE="1"/>
        <PARAMETER NAME="CLKOUT5_SEQUENCE_NUMBER" VALUE="1"/>
        <PARAMETER NAME="CLKOUT6_SEQUENCE_NUMBER" VALUE="1"/>
        <PARAMETER NAME="CLKOUT7_SEQUENCE_NUMBER" VALUE="1"/>
        <PARAMETER NAME="USE_BOARD_FLOW" VALUE="false"/>
        <PARAMETER NAME="CLK_IN1_BOARD_INTERFACE" VALUE="Custom"/>
        <PARAMETER NAME="CLK_IN2_BOARD_INTERFACE" VALUE="Custom"/>
        <PARAMETER NAME="DIFF_CLK_IN1_BOARD_INTERFACE" VALUE="Custom"/>
        <PARAMETER NAME="DIFF_CLK_IN2_BOARD_INTERFACE" VALUE="Custom"/>
        <PARAMETER NAME="AUTO_PRIMITIVE" VALUE="MMCM"/>
        <PARAMETER NAME="RESET_BOARD_INTERFACE" VALUE="Custom"/>
        <PARAMETER NAME="ENABLE_CDDC" VALUE="false"/>
        <PARAMETER NAME="CDDCDONE_PORT" VALUE="cddcdone"/>
        <PARAMETER NAME="CDDCREQ_PORT" VALUE="cddcreq"/>
        <PARAMETER NAME="ENABLE_CLKOUTPHY" VALUE="false"/>
        <PARAMETER NAME="CLKOUTPHY_REQUESTED_FREQ" VALUE="600.000"/>
        <PARAMETER NAME="CLKOUT1_JITTER" VALUE="121.076"/>
        <PARAMETER NAME="CLKOUT1_PHASE_ERROR" VALUE="98.137"/>
        <PARAMETER NAME="CLKOUT2_JITTER" VALUE="106.280"/>
        <PARAMETER NAME="CLKOUT2_PHASE_ERROR" VALUE="98.137"/>
        <PARAMETER NAME="CLKOUT3_JITTER" VALUE="106.280"/>
        <PARAMETER NAME="CLKOUT3_PHASE_ERROR" VALUE="98.137"/>
        <PARAMETER NAME="CLKOUT4_JITTER" VALUE="0.0"/>
        <PARAMETER NAME="CLKOUT4_PHASE_ERROR" VALUE="0.0"/>
        <PARAMETER NAME="CLKOUT5_JITTER" VALUE="0.0"/>
        <PARAMETER NAME="CLKOUT5_PHASE_ERROR" VALUE="0.0"/>
        <PARAMETER NAME="CLKOUT6_JITTER" VALUE="0.0"/>
        <PARAMETER NAME="CLKOUT6_PHASE_ERROR" VALUE="0.0"/>
        <PARAMETER NAME="CLKOUT7_JITTER" VALUE="0.0"/>
        <PARAMETER NAME="CLKOUT7_PHASE_ERROR" VALUE="0.0"/>
        <PARAMETER NAME="INPUT_MODE" VALUE="frequency"/>
        <PARAMETER NAME="INTERFACE_SELECTION" VALUE="Enable_AXI"/>
        <PARAMETER NAME="AXI_DRP" VALUE="false"/>
        <PARAMETER NAME="PHASE_DUTY_CONFIG" VALUE="false"/>
        <PARAMETER NAME="EDK_IPTYPE" VALUE="PERIPHERAL"/>
      </PARAMETERS>
      <PORTS>
        <PORT DIR="I" NAME="clk_in1_p" SIGIS="clk" SIGNAME="External_Ports_adc_clk_p_i">
          <CONNECTIONS>
            <CONNECTION INSTANCE="External_Ports" PORT="adc_clk_p_i"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" NAME="clk_in1_n" SIGIS="clk" SIGNAME="External_Ports_adc_clk_n_i">
          <CONNECTIONS>
            <CONNECTION INSTANCE="External_Ports" PORT="adc_clk_n_i"/>
          </CONNECTIONS>
        </PORT>
        <PORT CLKFREQUENCY="122880000" DIR="O" NAME="clk_out1" SIGIS="clk" SIGNAME="pll_0_clk_out1">
          <CONNECTIONS>
            <CONNECTION INSTANCE="ps_0" PORT="M_AXI_GP0_ACLK"/>
            <CONNECTION INSTANCE="ps_0" PORT="S_AXI_ACP_ACLK"/>
            <CONNECTION INSTANCE="rst_0" PORT="slowest_sync_clk"/>
            <CONNECTION INSTANCE="adc_0" PORT="aclk"/>
            <CONNECTION INSTANCE="dac_0" PORT="aclk"/>
            <CONNECTION INSTANCE="hub_0" PORT="aclk"/>
            <CONNECTION INSTANCE="dds_0" PORT="aclk"/>
            <CONNECTION INSTANCE="dds_1" PORT="aclk"/>
            <CONNECTION INSTANCE="dds_2" PORT="aclk"/>
            <CONNECTION INSTANCE="dds_3" PORT="aclk"/>
            <CONNECTION INSTANCE="mult_0" PORT="CLK"/>
            <CONNECTION INSTANCE="rate_0" PORT="aclk"/>
            <CONNECTION INSTANCE="cic_0" PORT="aclk"/>
            <CONNECTION INSTANCE="mult_1" PORT="CLK"/>
            <CONNECTION INSTANCE="rate_1" PORT="aclk"/>
            <CONNECTION INSTANCE="cic_1" PORT="aclk"/>
            <CONNECTION INSTANCE="mult_2" PORT="CLK"/>
            <CONNECTION INSTANCE="rate_2" PORT="aclk"/>
            <CONNECTION INSTANCE="cic_2" PORT="aclk"/>
            <CONNECTION INSTANCE="mult_3" PORT="CLK"/>
            <CONNECTION INSTANCE="rate_3" PORT="aclk"/>
            <CONNECTION INSTANCE="cic_3" PORT="aclk"/>
            <CONNECTION INSTANCE="comb_0" PORT="aclk"/>
            <CONNECTION INSTANCE="fir_0" PORT="aclk"/>
            <CONNECTION INSTANCE="subset_0" PORT="aclk"/>
            <CONNECTION INSTANCE="writer_0" PORT="aclk"/>
            <CONNECTION INSTANCE="mult_4" PORT="CLK"/>
            <CONNECTION INSTANCE="mult_5" PORT="CLK"/>
            <CONNECTION INSTANCE="fsk_detector_1_00_0" PORT="aclk"/>
          </CONNECTIONS>
        </PORT>
        <PORT CLKFREQUENCY="245760000" DIR="O" NAME="clk_out2" SIGIS="clk" SIGNAME="pll_0_clk_out2">
          <CONNECTIONS>
            <CONNECTION INSTANCE="dac_0" PORT="ddr_clk"/>
          </CONNECTIONS>
        </PORT>
        <PORT CLKFREQUENCY="245760000" DIR="O" NAME="clk_out3" SIGIS="clk" SIGNAME="pll_0_clk_out3">
          <CONNECTIONS>
            <CONNECTION INSTANCE="dac_0" PORT="wrt_clk"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" NAME="locked" SIGIS="undef" SIGNAME="pll_0_locked">
          <CONNECTIONS>
            <CONNECTION INSTANCE="rst_0" PORT="dcm_locked"/>
            <CONNECTION INSTANCE="dac_0" PORT="locked"/>
          </CONNECTIONS>
        </PORT>
      </PORTS>
      <BUSINTERFACES>
        <BUSINTERFACE BUSNAME="__NOC__" NAME="CLK_IN1_D" TYPE="TARGET" VLNV="xilinx.com:interface:diff_clock:1.0">
          <PARAMETER NAME="CAN_DEBUG" VALUE="false"/>
          <PARAMETER NAME="FREQ_HZ" VALUE="122880000"/>
          <PORTMAPS>
            <PORTMAP LOGICAL="CLK_N" PHYSICAL="clk_in1_n"/>
            <PORTMAP LOGICAL="CLK_P" PHYSICAL="clk_in1_p"/>
          </PORTMAPS>
        </BUSINTERFACE>
      </BUSINTERFACES>
    </MODULE>
    <MODULE CONFIGURABLE="TRUE" COREREVISION="6" FULLNAME="/ps_0" HWVERSION="5.5" INSTANCE="ps_0" IPTYPE="PERIPHERAL" IS_ENABLE="1" IS_PL="FALSE" MODTYPE="processing_system7" VLNV="xilinx.com:ip:processing_system7:5.5">
      <DOCUMENTS>
        <DOCUMENT SOURCE="http://www.xilinx.com/cgi-bin/docs/ipdoc?c=processing_system7;v=v5_3;d=pg082-processing-system7.pdf"/>
      </DOCUMENTS>
      <PARAMETERS>
        <PARAMETER NAME="C_EN_EMIO_PJTAG" VALUE="0"/>
        <PARAMETER NAME="C_EN_EMIO_ENET0" VALUE="0"/>
        <PARAMETER NAME="C_EN_EMIO_ENET1" VALUE="0"/>
        <PARAMETER NAME="C_EN_EMIO_TRACE" VALUE="0"/>
        <PARAMETER NAME="C_INCLUDE_TRACE_BUFFER" VALUE="0"/>
        <PARAMETER NAME="C_TRACE_BUFFER_FIFO_SIZE" VALUE="128"/>
        <PARAMETER NAME="USE_TRACE_DATA_EDGE_DETECTOR" VALUE="0"/>
        <PARAMETER NAME="C_TRACE_PIPELINE_WIDTH" VALUE="8"/>
        <PARAMETER NAME="C_TRACE_BUFFER_CLOCK_DELAY" VALUE="12"/>
        <PARAMETER NAME="C_EMIO_GPIO_WIDTH" VALUE="64"/>
        <PARAMETER NAME="C_INCLUDE_ACP_TRANS_CHECK" VALUE="0"/>
        <PARAMETER NAME="C_USE_DEFAULT_ACP_USER_VAL" VALUE="1"/>
        <PARAMETER NAME="C_S_AXI_ACP_ARUSER_VAL" VALUE="31"/>
        <PARAMETER NAME="C_S_AXI_ACP_AWUSER_VAL" VALUE="31"/>
        <PARAMETER NAME="C_M_AXI_GP0_ID_WIDTH" VALUE="12"/>
        <PARAMETER NAME="C_M_AXI_GP0_ENABLE_STATIC_REMAP" VALUE="0"/>
        <PARAMETER NAME="C_M_AXI_GP1_ID_WIDTH" VALUE="12"/>
        <PARAMETER NAME="C_M_AXI_GP1_ENABLE_STATIC_REMAP" VALUE="0"/>
        <PARAMETER NAME="C_S_AXI_GP0_ID_WIDTH" VALUE="6"/>
        <PARAMETER NAME="C_S_AXI_GP1_ID_WIDTH" VALUE="6"/>
        <PARAMETER NAME="C_S_AXI_ACP_ID_WIDTH" VALUE="3"/>
        <PARAMETER NAME="C_S_AXI_HP0_ID_WIDTH" VALUE="6"/>
        <PARAMETER NAME="C_S_AXI_HP0_DATA_WIDTH" VALUE="64"/>
        <PARAMETER NAME="C_S_AXI_HP1_ID_WIDTH" VALUE="6"/>
        <PARAMETER NAME="C_S_AXI_HP1_DATA_WIDTH" VALUE="64"/>
        <PARAMETER NAME="C_S_AXI_HP2_ID_WIDTH" VALUE="6"/>
        <PARAMETER NAME="C_S_AXI_HP2_DATA_WIDTH" VALUE="64"/>
        <PARAMETER NAME="C_S_AXI_HP3_ID_WIDTH" VALUE="6"/>
        <PARAMETER NAME="C_S_AXI_HP3_DATA_WIDTH" VALUE="64"/>
        <PARAMETER NAME="C_M_AXI_GP0_THREAD_ID_WIDTH" VALUE="12"/>
        <PARAMETER NAME="C_M_AXI_GP1_THREAD_ID_WIDTH" VALUE="12"/>
        <PARAMETER NAME="C_NUM_F2P_INTR_INPUTS" VALUE="1"/>
        <PARAMETER NAME="C_IRQ_F2P_MODE" VALUE="DIRECT"/>
        <PARAMETER NAME="C_DQ_WIDTH" VALUE="32"/>
        <PARAMETER NAME="C_DQS_WIDTH" VALUE="4"/>
        <PARAMETER NAME="C_DM_WIDTH" VALUE="4"/>
        <PARAMETER NAME="C_MIO_PRIMITIVE" VALUE="54"/>
        <PARAMETER NAME="C_TRACE_INTERNAL_WIDTH" VALUE="2"/>
        <PARAMETER NAME="C_USE_AXI_NONSECURE" VALUE="0"/>
        <PARAMETER NAME="C_USE_M_AXI_GP0" VALUE="1"/>
        <PARAMETER NAME="C_USE_M_AXI_GP1" VALUE="0"/>
        <PARAMETER NAME="C_USE_S_AXI_GP0" VALUE="0"/>
        <PARAMETER NAME="C_USE_S_AXI_GP1" VALUE="0"/>
        <PARAMETER NAME="C_USE_S_AXI_HP0" VALUE="0"/>
        <PARAMETER NAME="C_USE_S_AXI_HP1" VALUE="0"/>
        <PARAMETER NAME="C_USE_S_AXI_HP2" VALUE="0"/>
        <PARAMETER NAME="C_USE_S_AXI_HP3" VALUE="0"/>
        <PARAMETER NAME="C_USE_S_AXI_ACP" VALUE="1"/>
        <PARAMETER NAME="C_PS7_SI_REV" VALUE="PRODUCTION"/>
        <PARAMETER NAME="C_FCLK_CLK0_BUF" VALUE="TRUE"/>
        <PARAMETER NAME="C_FCLK_CLK1_BUF" VALUE="FALSE"/>
        <PARAMETER NAME="C_FCLK_CLK2_BUF" VALUE="FALSE"/>
        <PARAMETER NAME="C_FCLK_CLK3_BUF" VALUE="FALSE"/>
        <PARAMETER NAME="C_PACKAGE_NAME" VALUE="clg400"/>
        <PARAMETER NAME="C_GP0_EN_MODIFIABLE_TXN" VALUE="1"/>
        <PARAMETER NAME="C_GP1_EN_MODIFIABLE_TXN" VALUE="1"/>
        <PARAMETER NAME="PCW_DDR_RAM_BASEADDR" VALUE="0x00100000"/>
        <PARAMETER NAME="PCW_DDR_RAM_HIGHADDR" VALUE="0x1FFFFFFF"/>
        <PARAMETER NAME="PCW_UART0_BASEADDR" VALUE="0xE0000000"/>
        <PARAMETER NAME="PCW_UART0_HIGHADDR" VALUE="0xE0000FFF"/>
        <PARAMETER NAME="PCW_UART1_BASEADDR" VALUE="0xE0001000"/>
        <PARAMETER NAME="PCW_UART1_HIGHADDR" VALUE="0xE0001FFF"/>
        <PARAMETER NAME="PCW_I2C0_BASEADDR" VALUE="0xE0004000"/>
        <PARAMETER NAME="PCW_I2C0_HIGHADDR" VALUE="0xE0004FFF"/>
        <PARAMETER NAME="PCW_I2C1_BASEADDR" VALUE="0xE0005000"/>
        <PARAMETER NAME="PCW_I2C1_HIGHADDR" VALUE="0xE0005FFF"/>
        <PARAMETER NAME="PCW_SPI0_BASEADDR" VALUE="0xE0006000"/>
        <PARAMETER NAME="PCW_SPI0_HIGHADDR" VALUE="0xE0006FFF"/>
        <PARAMETER NAME="PCW_SPI1_BASEADDR" VALUE="0xE0007000"/>
        <PARAMETER NAME="PCW_SPI1_HIGHADDR" VALUE="0xE0007FFF"/>
        <PARAMETER NAME="PCW_CAN0_BASEADDR" VALUE="0xE0008000"/>
        <PARAMETER NAME="PCW_CAN0_HIGHADDR" VALUE="0xE0008FFF"/>
        <PARAMETER NAME="PCW_CAN1_BASEADDR" VALUE="0xE0009000"/>
        <PARAMETER NAME="PCW_CAN1_HIGHADDR" VALUE="0xE0009FFF"/>
        <PARAMETER NAME="PCW_GPIO_BASEADDR" VALUE="0xE000A000"/>
        <PARAMETER NAME="PCW_GPIO_HIGHADDR" VALUE="0xE000AFFF"/>
        <PARAMETER NAME="PCW_ENET0_BASEADDR" VALUE="0xE000B000"/>
        <PARAMETER NAME="PCW_ENET0_HIGHADDR" VALUE="0xE000BFFF"/>
        <PARAMETER NAME="PCW_ENET1_BASEADDR" VALUE="0xE000C000"/>
        <PARAMETER NAME="PCW_ENET1_HIGHADDR" VALUE="0xE000CFFF"/>
        <PARAMETER NAME="PCW_SDIO0_BASEADDR" VALUE="0xE0100000"/>
        <PARAMETER NAME="PCW_SDIO0_HIGHADDR" VALUE="0xE0100FFF"/>
        <PARAMETER NAME="PCW_SDIO1_BASEADDR" VALUE="0xE0101000"/>
        <PARAMETER NAME="PCW_SDIO1_HIGHADDR" VALUE="0xE0101FFF"/>
        <PARAMETER NAME="PCW_USB0_BASEADDR" VALUE="0xE0102000"/>
        <PARAMETER NAME="PCW_USB0_HIGHADDR" VALUE="0xE0102fff"/>
        <PARAMETER NAME="PCW_USB1_BASEADDR" VALUE="0xE0103000"/>
        <PARAMETER NAME="PCW_USB1_HIGHADDR" VALUE="0xE0103fff"/>
        <PARAMETER NAME="PCW_TTC0_BASEADDR" VALUE="0xE0104000"/>
        <PARAMETER NAME="PCW_TTC0_HIGHADDR" VALUE="0xE0104fff"/>
        <PARAMETER NAME="PCW_TTC1_BASEADDR" VALUE="0xE0105000"/>
        <PARAMETER NAME="PCW_TTC1_HIGHADDR" VALUE="0xE0105fff"/>
        <PARAMETER NAME="PCW_FCLK_CLK0_BUF" VALUE="TRUE"/>
        <PARAMETER NAME="PCW_FCLK_CLK1_BUF" VALUE="FALSE"/>
        <PARAMETER NAME="PCW_FCLK_CLK2_BUF" VALUE="FALSE"/>
        <PARAMETER NAME="PCW_FCLK_CLK3_BUF" VALUE="FALSE"/>
        <PARAMETER NAME="PCW_UIPARAM_DDR_FREQ_MHZ" VALUE="533.333333"/>
        <PARAMETER NAME="PCW_UIPARAM_DDR_BANK_ADDR_COUNT" VALUE="3"/>
        <PARAMETER NAME="PCW_UIPARAM_DDR_ROW_ADDR_COUNT" VALUE="15"/>
        <PARAMETER NAME="PCW_UIPARAM_DDR_COL_ADDR_COUNT" VALUE="10"/>
        <PARAMETER NAME="PCW_UIPARAM_DDR_CL" VALUE="7"/>
        <PARAMETER NAME="PCW_UIPARAM_DDR_CWL" VALUE="6"/>
        <PARAMETER NAME="PCW_UIPARAM_DDR_T_RCD" VALUE="7"/>
        <PARAMETER NAME="PCW_UIPARAM_DDR_T_RP" VALUE="7"/>
        <PARAMETER NAME="PCW_UIPARAM_DDR_T_RC" VALUE="48.91"/>
        <PARAMETER NAME="PCW_UIPARAM_DDR_T_RAS_MIN" VALUE="35.0"/>
        <PARAMETER NAME="PCW_UIPARAM_DDR_T_FAW" VALUE="40.0"/>
        <PARAMETER NAME="PCW_UIPARAM_DDR_AL" VALUE="0"/>
        <PARAMETER NAME="PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_0" VALUE="0.0"/>
        <PARAMETER NAME="PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_1" VALUE="0.0"/>
        <PARAMETER NAME="PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_2" VALUE="0.0"/>
        <PARAMETER NAME="PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_3" VALUE="0.0"/>
        <PARAMETER NAME="PCW_UIPARAM_DDR_BOARD_DELAY0" VALUE="0.25"/>
        <PARAMETER NAME="PCW_UIPARAM_DDR_BOARD_DELAY1" VALUE="0.25"/>
        <PARAMETER NAME="PCW_UIPARAM_DDR_BOARD_DELAY2" VALUE="0.25"/>
        <PARAMETER NAME="PCW_UIPARAM_DDR_BOARD_DELAY3" VALUE="0.25"/>
        <PARAMETER NAME="PCW_UIPARAM_DDR_DQS_0_LENGTH_MM" VALUE="0"/>
        <PARAMETER NAME="PCW_UIPARAM_DDR_DQS_1_LENGTH_MM" VALUE="0"/>
        <PARAMETER NAME="PCW_UIPARAM_DDR_DQS_2_LENGTH_MM" VALUE="0"/>
        <PARAMETER NAME="PCW_UIPARAM_DDR_DQS_3_LENGTH_MM" VALUE="0"/>
        <PARAMETER NAME="PCW_UIPARAM_DDR_DQ_0_LENGTH_MM" VALUE="0"/>
        <PARAMETER NAME="PCW_UIPARAM_DDR_DQ_1_LENGTH_MM" VALUE="0"/>
        <PARAMETER NAME="PCW_UIPARAM_DDR_DQ_2_LENGTH_MM" VALUE="0"/>
        <PARAMETER NAME="PCW_UIPARAM_DDR_DQ_3_LENGTH_MM" VALUE="0"/>
        <PARAMETER NAME="PCW_UIPARAM_DDR_CLOCK_0_LENGTH_MM" VALUE="0"/>
        <PARAMETER NAME="PCW_UIPARAM_DDR_CLOCK_1_LENGTH_MM" VALUE="0"/>
        <PARAMETER NAME="PCW_UIPARAM_DDR_CLOCK_2_LENGTH_MM" VALUE="0"/>
        <PARAMETER NAME="PCW_UIPARAM_DDR_CLOCK_3_LENGTH_MM" VALUE="0"/>
        <PARAMETER NAME="PCW_UIPARAM_DDR_DQS_0_PACKAGE_LENGTH" VALUE="105.056"/>
        <PARAMETER NAME="PCW_UIPARAM_DDR_DQS_1_PACKAGE_LENGTH" VALUE="66.904"/>
        <PARAMETER NAME="PCW_UIPARAM_DDR_DQS_2_PACKAGE_LENGTH" VALUE="89.1715"/>
        <PARAMETER NAME="PCW_UIPARAM_DDR_DQS_3_PACKAGE_LENGTH" VALUE="113.63"/>
        <PARAMETER NAME="PCW_UIPARAM_DDR_DQ_0_PACKAGE_LENGTH" VALUE="98.503"/>
        <PARAMETER NAME="PCW_UIPARAM_DDR_DQ_1_PACKAGE_LENGTH" VALUE="68.5855"/>
        <PARAMETER NAME="PCW_UIPARAM_DDR_DQ_2_PACKAGE_LENGTH" VALUE="90.295"/>
        <PARAMETER NAME="PCW_UIPARAM_DDR_DQ_3_PACKAGE_LENGTH" VALUE="103.977"/>
        <PARAMETER NAME="PCW_UIPARAM_DDR_CLOCK_0_PACKAGE_LENGTH" VALUE="80.4535"/>
        <PARAMETER NAME="PCW_UIPARAM_DDR_CLOCK_1_PACKAGE_LENGTH" VALUE="80.4535"/>
        <PARAMETER NAME="PCW_UIPARAM_DDR_CLOCK_2_PACKAGE_LENGTH" VALUE="80.4535"/>
        <PARAMETER NAME="PCW_UIPARAM_DDR_CLOCK_3_PACKAGE_LENGTH" VALUE="80.4535"/>
        <PARAMETER NAME="PCW_UIPARAM_DDR_DQS_0_PROPOGATION_DELAY" VALUE="160"/>
        <PARAMETER NAME="PCW_UIPARAM_DDR_DQS_1_PROPOGATION_DELAY" VALUE="160"/>
        <PARAMETER NAME="PCW_UIPARAM_DDR_DQS_2_PROPOGATION_DELAY" VALUE="160"/>
        <PARAMETER NAME="PCW_UIPARAM_DDR_DQS_3_PROPOGATION_DELAY" VALUE="160"/>
        <PARAMETER NAME="PCW_UIPARAM_DDR_DQ_0_PROPOGATION_DELAY" VALUE="160"/>
        <PARAMETER NAME="PCW_UIPARAM_DDR_DQ_1_PROPOGATION_DELAY" VALUE="160"/>
        <PARAMETER NAME="PCW_UIPARAM_DDR_DQ_2_PROPOGATION_DELAY" VALUE="160"/>
        <PARAMETER NAME="PCW_UIPARAM_DDR_DQ_3_PROPOGATION_DELAY" VALUE="160"/>
        <PARAMETER NAME="PCW_UIPARAM_DDR_CLOCK_0_PROPOGATION_DELAY" VALUE="160"/>
        <PARAMETER NAME="PCW_UIPARAM_DDR_CLOCK_1_PROPOGATION_DELAY" VALUE="160"/>
        <PARAMETER NAME="PCW_UIPARAM_DDR_CLOCK_2_PROPOGATION_DELAY" VALUE="160"/>
        <PARAMETER NAME="PCW_UIPARAM_DDR_CLOCK_3_PROPOGATION_DELAY" VALUE="160"/>
        <PARAMETER NAME="PCW_PACKAGE_DDR_DQS_TO_CLK_DELAY_0" VALUE="-0.025"/>
        <PARAMETER NAME="PCW_PACKAGE_DDR_DQS_TO_CLK_DELAY_1" VALUE="0.014"/>
        <PARAMETER NAME="PCW_PACKAGE_DDR_DQS_TO_CLK_DELAY_2" VALUE="-0.009"/>
        <PARAMETER NAME="PCW_PACKAGE_DDR_DQS_TO_CLK_DELAY_3" VALUE="-0.033"/>
        <PARAMETER NAME="PCW_PACKAGE_DDR_BOARD_DELAY0" VALUE="0.089"/>
        <PARAMETER NAME="PCW_PACKAGE_DDR_BOARD_DELAY1" VALUE="0.075"/>
        <PARAMETER NAME="PCW_PACKAGE_DDR_BOARD_DELAY2" VALUE="0.085"/>
        <PARAMETER NAME="PCW_PACKAGE_DDR_BOARD_DELAY3" VALUE="0.092"/>
        <PARAMETER NAME="PCW_CPU_CPU_6X4X_MAX_RANGE" VALUE="667"/>
        <PARAMETER NAME="PCW_CRYSTAL_PERIPHERAL_FREQMHZ" VALUE="33.333333"/>
        <PARAMETER NAME="PCW_APU_PERIPHERAL_FREQMHZ" VALUE="666.666666"/>
        <PARAMETER NAME="PCW_DCI_PERIPHERAL_FREQMHZ" VALUE="10.159"/>
        <PARAMETER NAME="PCW_QSPI_PERIPHERAL_FREQMHZ" VALUE="200"/>
        <PARAMETER NAME="PCW_SMC_PERIPHERAL_FREQMHZ" VALUE="100"/>
        <PARAMETER NAME="PCW_USB0_PERIPHERAL_FREQMHZ" VALUE="60"/>
        <PARAMETER NAME="PCW_USB1_PERIPHERAL_FREQMHZ" VALUE="60"/>
        <PARAMETER NAME="PCW_SDIO_PERIPHERAL_FREQMHZ" VALUE="100"/>
        <PARAMETER NAME="PCW_UART_PERIPHERAL_FREQMHZ" VALUE="100"/>
        <PARAMETER NAME="PCW_SPI_PERIPHERAL_FREQMHZ" VALUE="166.666666"/>
        <PARAMETER NAME="PCW_CAN_PERIPHERAL_FREQMHZ" VALUE="100"/>
        <PARAMETER NAME="PCW_CAN0_PERIPHERAL_FREQMHZ" VALUE="-1"/>
        <PARAMETER NAME="PCW_CAN1_PERIPHERAL_FREQMHZ" VALUE="-1"/>
        <PARAMETER NAME="PCW_I2C_PERIPHERAL_FREQMHZ" VALUE="111.111115"/>
        <PARAMETER NAME="PCW_WDT_PERIPHERAL_FREQMHZ" VALUE="133.333333"/>
        <PARAMETER NAME="PCW_TTC_PERIPHERAL_FREQMHZ" VALUE="50"/>
        <PARAMETER NAME="PCW_TTC0_CLK0_PERIPHERAL_FREQMHZ" VALUE="133.333333"/>
        <PARAMETER NAME="PCW_TTC0_CLK1_PERIPHERAL_FREQMHZ" VALUE="133.333333"/>
        <PARAMETER NAME="PCW_TTC0_CLK2_PERIPHERAL_FREQMHZ" VALUE="133.333333"/>
        <PARAMETER NAME="PCW_TTC1_CLK0_PERIPHERAL_FREQMHZ" VALUE="133.333333"/>
        <PARAMETER NAME="PCW_TTC1_CLK1_PERIPHERAL_FREQMHZ" VALUE="133.333333"/>
        <PARAMETER NAME="PCW_TTC1_CLK2_PERIPHERAL_FREQMHZ" VALUE="133.333333"/>
        <PARAMETER NAME="PCW_PCAP_PERIPHERAL_FREQMHZ" VALUE="200"/>
        <PARAMETER NAME="PCW_TPIU_PERIPHERAL_FREQMHZ" VALUE="200"/>
        <PARAMETER NAME="PCW_FPGA0_PERIPHERAL_FREQMHZ" VALUE="50"/>
        <PARAMETER NAME="PCW_FPGA1_PERIPHERAL_FREQMHZ" VALUE="50"/>
        <PARAMETER NAME="PCW_FPGA2_PERIPHERAL_FREQMHZ" VALUE="50"/>
        <PARAMETER NAME="PCW_FPGA3_PERIPHERAL_FREQMHZ" VALUE="50"/>
        <PARAMETER NAME="PCW_ACT_APU_PERIPHERAL_FREQMHZ" VALUE="666.666687"/>
        <PARAMETER NAME="PCW_UIPARAM_ACT_DDR_FREQ_MHZ" VALUE="533.333374"/>
        <PARAMETER NAME="PCW_ACT_DCI_PERIPHERAL_FREQMHZ" VALUE="10.158730"/>
        <PARAMETER NAME="PCW_ACT_QSPI_PERIPHERAL_FREQMHZ" VALUE="10.000000"/>
        <PARAMETER NAME="PCW_ACT_SMC_PERIPHERAL_FREQMHZ" VALUE="10.000000"/>
        <PARAMETER NAME="PCW_ACT_ENET0_PERIPHERAL_FREQMHZ" VALUE="125.000000"/>
        <PARAMETER NAME="PCW_ACT_ENET1_PERIPHERAL_FREQMHZ" VALUE="10.000000"/>
        <PARAMETER NAME="PCW_ACT_USB0_PERIPHERAL_FREQMHZ" VALUE="60"/>
        <PARAMETER NAME="PCW_ACT_USB1_PERIPHERAL_FREQMHZ" VALUE="60"/>
        <PARAMETER NAME="PCW_ACT_SDIO_PERIPHERAL_FREQMHZ" VALUE="100.000000"/>
        <PARAMETER NAME="PCW_ACT_UART_PERIPHERAL_FREQMHZ" VALUE="100.000000"/>
        <PARAMETER NAME="PCW_ACT_SPI_PERIPHERAL_FREQMHZ" VALUE="166.666672"/>
        <PARAMETER NAME="PCW_ACT_CAN_PERIPHERAL_FREQMHZ" VALUE="10.000000"/>
        <PARAMETER NAME="PCW_ACT_CAN0_PERIPHERAL_FREQMHZ" VALUE="23.8095"/>
        <PARAMETER NAME="PCW_ACT_CAN1_PERIPHERAL_FREQMHZ" VALUE="23.8095"/>
        <PARAMETER NAME="PCW_ACT_I2C_PERIPHERAL_FREQMHZ" VALUE="50"/>
        <PARAMETER NAME="PCW_ACT_WDT_PERIPHERAL_FREQMHZ" VALUE="111.111115"/>
        <PARAMETER NAME="PCW_ACT_TTC_PERIPHERAL_FREQMHZ" VALUE="50"/>
        <PARAMETER NAME="PCW_ACT_PCAP_PERIPHERAL_FREQMHZ" VALUE="200.000000"/>
        <PARAMETER NAME="PCW_ACT_TPIU_PERIPHERAL_FREQMHZ" VALUE="200.000000"/>
        <PARAMETER NAME="PCW_ACT_FPGA0_PERIPHERAL_FREQMHZ" VALUE="50.000000"/>
        <PARAMETER NAME="PCW_ACT_FPGA1_PERIPHERAL_FREQMHZ" VALUE="10.000000"/>
        <PARAMETER NAME="PCW_ACT_FPGA2_PERIPHERAL_FREQMHZ" VALUE="10.000000"/>
        <PARAMETER NAME="PCW_ACT_FPGA3_PERIPHERAL_FREQMHZ" VALUE="10.000000"/>
        <PARAMETER NAME="PCW_ACT_TTC0_CLK0_PERIPHERAL_FREQMHZ" VALUE="111.111115"/>
        <PARAMETER NAME="PCW_ACT_TTC0_CLK1_PERIPHERAL_FREQMHZ" VALUE="111.111115"/>
        <PARAMETER NAME="PCW_ACT_TTC0_CLK2_PERIPHERAL_FREQMHZ" VALUE="111.111115"/>
        <PARAMETER NAME="PCW_ACT_TTC1_CLK0_PERIPHERAL_FREQMHZ" VALUE="111.111115"/>
        <PARAMETER NAME="PCW_ACT_TTC1_CLK1_PERIPHERAL_FREQMHZ" VALUE="111.111115"/>
        <PARAMETER NAME="PCW_ACT_TTC1_CLK2_PERIPHERAL_FREQMHZ" VALUE="111.111115"/>
        <PARAMETER NAME="PCW_CLK0_FREQ" VALUE="50000000"/>
        <PARAMETER NAME="PCW_CLK1_FREQ" VALUE="10000000"/>
        <PARAMETER NAME="PCW_CLK2_FREQ" VALUE="10000000"/>
        <PARAMETER NAME="PCW_CLK3_FREQ" VALUE="10000000"/>
        <PARAMETER NAME="PCW_OVERRIDE_BASIC_CLOCK" VALUE="0"/>
        <PARAMETER NAME="PCW_CPU_PERIPHERAL_DIVISOR0" VALUE="2"/>
        <PARAMETER NAME="PCW_DDR_PERIPHERAL_DIVISOR0" VALUE="2"/>
        <PARAMETER NAME="PCW_SMC_PERIPHERAL_DIVISOR0" VALUE="1"/>
        <PARAMETER NAME="PCW_QSPI_PERIPHERAL_DIVISOR0" VALUE="1"/>
        <PARAMETER NAME="PCW_SDIO_PERIPHERAL_DIVISOR0" VALUE="10"/>
        <PARAMETER NAME="PCW_UART_PERIPHERAL_DIVISOR0" VALUE="10"/>
        <PARAMETER NAME="PCW_SPI_PERIPHERAL_DIVISOR0" VALUE="6"/>
        <PARAMETER NAME="PCW_CAN_PERIPHERAL_DIVISOR0" VALUE="1"/>
        <PARAMETER NAME="PCW_CAN_PERIPHERAL_DIVISOR1" VALUE="1"/>
        <PARAMETER NAME="PCW_FCLK0_PERIPHERAL_DIVISOR0" VALUE="5"/>
        <PARAMETER NAME="PCW_FCLK1_PERIPHERAL_DIVISOR0" VALUE="1"/>
        <PARAMETER NAME="PCW_FCLK2_PERIPHERAL_DIVISOR0" VALUE="1"/>
        <PARAMETER NAME="PCW_FCLK3_PERIPHERAL_DIVISOR0" VALUE="1"/>
        <PARAMETER NAME="PCW_FCLK0_PERIPHERAL_DIVISOR1" VALUE="4"/>
        <PARAMETER NAME="PCW_FCLK1_PERIPHERAL_DIVISOR1" VALUE="1"/>
        <PARAMETER NAME="PCW_FCLK2_PERIPHERAL_DIVISOR1" VALUE="1"/>
        <PARAMETER NAME="PCW_FCLK3_PERIPHERAL_DIVISOR1" VALUE="1"/>
        <PARAMETER NAME="PCW_ENET0_PERIPHERAL_DIVISOR0" VALUE="8"/>
        <PARAMETER NAME="PCW_ENET1_PERIPHERAL_DIVISOR0" VALUE="1"/>
        <PARAMETER NAME="PCW_ENET0_PERIPHERAL_DIVISOR1" VALUE="1"/>
        <PARAMETER NAME="PCW_ENET1_PERIPHERAL_DIVISOR1" VALUE="1"/>
        <PARAMETER NAME="PCW_TPIU_PERIPHERAL_DIVISOR0" VALUE="1"/>
        <PARAMETER NAME="PCW_DCI_PERIPHERAL_DIVISOR0" VALUE="15"/>
        <PARAMETER NAME="PCW_DCI_PERIPHERAL_DIVISOR1" VALUE="7"/>
        <PARAMETER NAME="PCW_PCAP_PERIPHERAL_DIVISOR0" VALUE="5"/>
        <PARAMETER NAME="PCW_TTC0_CLK0_PERIPHERAL_DIVISOR0" VALUE="1"/>
        <PARAMETER NAME="PCW_TTC0_CLK1_PERIPHERAL_DIVISOR0" VALUE="1"/>
        <PARAMETER NAME="PCW_TTC0_CLK2_PERIPHERAL_DIVISOR0" VALUE="1"/>
        <PARAMETER NAME="PCW_TTC1_CLK0_PERIPHERAL_DIVISOR0" VALUE="1"/>
        <PARAMETER NAME="PCW_TTC1_CLK1_PERIPHERAL_DIVISOR0" VALUE="1"/>
        <PARAMETER NAME="PCW_TTC1_CLK2_PERIPHERAL_DIVISOR0" VALUE="1"/>
        <PARAMETER NAME="PCW_WDT_PERIPHERAL_DIVISOR0" VALUE="1"/>
        <PARAMETER NAME="PCW_ARMPLL_CTRL_FBDIV" VALUE="40"/>
        <PARAMETER NAME="PCW_IOPLL_CTRL_FBDIV" VALUE="30"/>
        <PARAMETER NAME="PCW_DDRPLL_CTRL_FBDIV" VALUE="32"/>
        <PARAMETER NAME="PCW_CPU_CPU_PLL_FREQMHZ" VALUE="1333.333"/>
        <PARAMETER NAME="PCW_IO_IO_PLL_FREQMHZ" VALUE="1000.000"/>
        <PARAMETER NAME="PCW_DDR_DDR_PLL_FREQMHZ" VALUE="1066.667"/>
        <PARAMETER NAME="PCW_SMC_PERIPHERAL_VALID" VALUE="0"/>
        <PARAMETER NAME="PCW_SDIO_PERIPHERAL_VALID" VALUE="1"/>
        <PARAMETER NAME="PCW_SPI_PERIPHERAL_VALID" VALUE="1"/>
        <PARAMETER NAME="PCW_CAN_PERIPHERAL_VALID" VALUE="0"/>
        <PARAMETER NAME="PCW_UART_PERIPHERAL_VALID" VALUE="1"/>
        <PARAMETER NAME="PCW_EN_EMIO_CAN0" VALUE="0"/>
        <PARAMETER NAME="PCW_EN_EMIO_CAN1" VALUE="0"/>
        <PARAMETER NAME="PCW_EN_EMIO_ENET0" VALUE="0"/>
        <PARAMETER NAME="PCW_EN_EMIO_ENET1" VALUE="0"/>
        <PARAMETER NAME="PCW_EN_PTP_ENET0" VALUE="0"/>
        <PARAMETER NAME="PCW_EN_PTP_ENET1" VALUE="0"/>
        <PARAMETER NAME="PCW_EN_EMIO_GPIO" VALUE="1"/>
        <PARAMETER NAME="PCW_EN_EMIO_I2C0" VALUE="0"/>
        <PARAMETER NAME="PCW_EN_EMIO_I2C1" VALUE="0"/>
        <PARAMETER NAME="PCW_EN_EMIO_PJTAG" VALUE="0"/>
        <PARAMETER NAME="PCW_EN_EMIO_SDIO0" VALUE="0"/>
        <PARAMETER NAME="PCW_EN_EMIO_CD_SDIO0" VALUE="0"/>
        <PARAMETER NAME="PCW_EN_EMIO_WP_SDIO0" VALUE="0"/>
        <PARAMETER NAME="PCW_EN_EMIO_SDIO1" VALUE="0"/>
        <PARAMETER NAME="PCW_EN_EMIO_CD_SDIO1" VALUE="0"/>
        <PARAMETER NAME="PCW_EN_EMIO_WP_SDIO1" VALUE="0"/>
        <PARAMETER NAME="PCW_EN_EMIO_SPI0" VALUE="1"/>
        <PARAMETER NAME="PCW_EN_EMIO_SPI1" VALUE="0"/>
        <PARAMETER NAME="PCW_EN_EMIO_UART0" VALUE="0"/>
        <PARAMETER NAME="PCW_EN_EMIO_UART1" VALUE="0"/>
        <PARAMETER NAME="PCW_EN_EMIO_MODEM_UART0" VALUE="0"/>
        <PARAMETER NAME="PCW_EN_EMIO_MODEM_UART1" VALUE="0"/>
        <PARAMETER NAME="PCW_EN_EMIO_TTC0" VALUE="0"/>
        <PARAMETER NAME="PCW_EN_EMIO_TTC1" VALUE="0"/>
        <PARAMETER NAME="PCW_EN_EMIO_WDT" VALUE="0"/>
        <PARAMETER NAME="PCW_EN_EMIO_TRACE" VALUE="0"/>
        <PARAMETER NAME="PCW_USE_AXI_NONSECURE" VALUE="0"/>
        <PARAMETER NAME="PCW_USE_M_AXI_GP0" VALUE="1"/>
        <PARAMETER NAME="PCW_USE_M_AXI_GP1" VALUE="0"/>
        <PARAMETER NAME="PCW_USE_S_AXI_GP0" VALUE="0"/>
        <PARAMETER NAME="PCW_USE_S_AXI_GP1" VALUE="0"/>
        <PARAMETER NAME="PCW_USE_S_AXI_ACP" VALUE="1"/>
        <PARAMETER NAME="PCW_USE_S_AXI_HP0" VALUE="0"/>
        <PARAMETER NAME="PCW_USE_S_AXI_HP1" VALUE="0"/>
        <PARAMETER NAME="PCW_USE_S_AXI_HP2" VALUE="0"/>
        <PARAMETER NAME="PCW_USE_S_AXI_HP3" VALUE="0"/>
        <PARAMETER NAME="PCW_M_AXI_GP0_FREQMHZ" VALUE="122"/>
        <PARAMETER NAME="PCW_M_AXI_GP1_FREQMHZ" VALUE="10"/>
        <PARAMETER NAME="PCW_S_AXI_GP0_FREQMHZ" VALUE="10"/>
        <PARAMETER NAME="PCW_S_AXI_GP1_FREQMHZ" VALUE="10"/>
        <PARAMETER NAME="PCW_S_AXI_ACP_FREQMHZ" VALUE="122"/>
        <PARAMETER NAME="PCW_S_AXI_HP0_FREQMHZ" VALUE="10"/>
        <PARAMETER NAME="PCW_S_AXI_HP1_FREQMHZ" VALUE="10"/>
        <PARAMETER NAME="PCW_S_AXI_HP2_FREQMHZ" VALUE="10"/>
        <PARAMETER NAME="PCW_S_AXI_HP3_FREQMHZ" VALUE="10"/>
        <PARAMETER NAME="PCW_USE_DMA0" VALUE="0"/>
        <PARAMETER NAME="PCW_USE_DMA1" VALUE="0"/>
        <PARAMETER NAME="PCW_USE_DMA2" VALUE="0"/>
        <PARAMETER NAME="PCW_USE_DMA3" VALUE="0"/>
        <PARAMETER NAME="PCW_USE_TRACE" VALUE="0"/>
        <PARAMETER NAME="PCW_TRACE_PIPELINE_WIDTH" VALUE="8"/>
        <PARAMETER NAME="PCW_INCLUDE_TRACE_BUFFER" VALUE="0"/>
        <PARAMETER NAME="PCW_TRACE_BUFFER_FIFO_SIZE" VALUE="128"/>
        <PARAMETER NAME="PCW_USE_TRACE_DATA_EDGE_DETECTOR" VALUE="0"/>
        <PARAMETER NAME="PCW_TRACE_BUFFER_CLOCK_DELAY" VALUE="12"/>
        <PARAMETER NAME="PCW_USE_CROSS_TRIGGER" VALUE="0"/>
        <PARAMETER NAME="PCW_FTM_CTI_IN0" VALUE="&lt;Select>"/>
        <PARAMETER NAME="PCW_FTM_CTI_IN1" VALUE="&lt;Select>"/>
        <PARAMETER NAME="PCW_FTM_CTI_IN2" VALUE="&lt;Select>"/>
        <PARAMETER NAME="PCW_FTM_CTI_IN3" VALUE="&lt;Select>"/>
        <PARAMETER NAME="PCW_FTM_CTI_OUT0" VALUE="&lt;Select>"/>
        <PARAMETER NAME="PCW_FTM_CTI_OUT1" VALUE="&lt;Select>"/>
        <PARAMETER NAME="PCW_FTM_CTI_OUT2" VALUE="&lt;Select>"/>
        <PARAMETER NAME="PCW_FTM_CTI_OUT3" VALUE="&lt;Select>"/>
        <PARAMETER NAME="PCW_USE_DEBUG" VALUE="0"/>
        <PARAMETER NAME="PCW_USE_CR_FABRIC" VALUE="1"/>
        <PARAMETER NAME="PCW_USE_AXI_FABRIC_IDLE" VALUE="0"/>
        <PARAMETER NAME="PCW_USE_DDR_BYPASS" VALUE="0"/>
        <PARAMETER NAME="PCW_USE_FABRIC_INTERRUPT" VALUE="0"/>
        <PARAMETER NAME="PCW_USE_PROC_EVENT_BUS" VALUE="0"/>
        <PARAMETER NAME="PCW_USE_EXPANDED_IOP" VALUE="0"/>
        <PARAMETER NAME="PCW_USE_HIGH_OCM" VALUE="0"/>
        <PARAMETER NAME="PCW_USE_PS_SLCR_REGISTERS" VALUE="0"/>
        <PARAMETER NAME="PCW_USE_EXPANDED_PS_SLCR_REGISTERS" VALUE="0"/>
        <PARAMETER NAME="PCW_USE_CORESIGHT" VALUE="0"/>
        <PARAMETER NAME="PCW_EN_EMIO_SRAM_INT" VALUE="0"/>
        <PARAMETER NAME="PCW_GPIO_EMIO_GPIO_WIDTH" VALUE="64"/>
        <PARAMETER NAME="PCW_GP0_NUM_WRITE_THREADS" VALUE="4"/>
        <PARAMETER NAME="PCW_GP0_NUM_READ_THREADS" VALUE="4"/>
        <PARAMETER NAME="PCW_GP1_NUM_WRITE_THREADS" VALUE="4"/>
        <PARAMETER NAME="PCW_GP1_NUM_READ_THREADS" VALUE="4"/>
        <PARAMETER NAME="PCW_UART0_BAUD_RATE" VALUE="115200"/>
        <PARAMETER NAME="PCW_UART1_BAUD_RATE" VALUE="115200"/>
        <PARAMETER NAME="PCW_EN_4K_TIMER" VALUE="0"/>
        <PARAMETER NAME="PCW_M_AXI_GP0_ID_WIDTH" VALUE="12"/>
        <PARAMETER NAME="PCW_M_AXI_GP0_ENABLE_STATIC_REMAP" VALUE="0"/>
        <PARAMETER NAME="PCW_M_AXI_GP0_SUPPORT_NARROW_BURST" VALUE="0"/>
        <PARAMETER NAME="PCW_M_AXI_GP0_THREAD_ID_WIDTH" VALUE="12"/>
        <PARAMETER NAME="PCW_M_AXI_GP1_ID_WIDTH" VALUE="12"/>
        <PARAMETER NAME="PCW_M_AXI_GP1_ENABLE_STATIC_REMAP" VALUE="0"/>
        <PARAMETER NAME="PCW_M_AXI_GP1_SUPPORT_NARROW_BURST" VALUE="0"/>
        <PARAMETER NAME="PCW_M_AXI_GP1_THREAD_ID_WIDTH" VALUE="12"/>
        <PARAMETER NAME="PCW_S_AXI_GP0_ID_WIDTH" VALUE="6"/>
        <PARAMETER NAME="PCW_S_AXI_GP1_ID_WIDTH" VALUE="6"/>
        <PARAMETER NAME="PCW_S_AXI_ACP_ID_WIDTH" VALUE="3"/>
        <PARAMETER NAME="PCW_INCLUDE_ACP_TRANS_CHECK" VALUE="0"/>
        <PARAMETER NAME="PCW_USE_DEFAULT_ACP_USER_VAL" VALUE="1"/>
        <PARAMETER NAME="PCW_S_AXI_ACP_ARUSER_VAL" VALUE="31"/>
        <PARAMETER NAME="PCW_S_AXI_ACP_AWUSER_VAL" VALUE="31"/>
        <PARAMETER NAME="PCW_S_AXI_HP0_ID_WIDTH" VALUE="6"/>
        <PARAMETER NAME="PCW_S_AXI_HP0_DATA_WIDTH" VALUE="64"/>
        <PARAMETER NAME="PCW_S_AXI_HP1_ID_WIDTH" VALUE="6"/>
        <PARAMETER NAME="PCW_S_AXI_HP1_DATA_WIDTH" VALUE="64"/>
        <PARAMETER NAME="PCW_S_AXI_HP2_ID_WIDTH" VALUE="6"/>
        <PARAMETER NAME="PCW_S_AXI_HP2_DATA_WIDTH" VALUE="64"/>
        <PARAMETER NAME="PCW_S_AXI_HP3_ID_WIDTH" VALUE="6"/>
        <PARAMETER NAME="PCW_S_AXI_HP3_DATA_WIDTH" VALUE="64"/>
        <PARAMETER NAME="PCW_NUM_F2P_INTR_INPUTS" VALUE="1"/>
        <PARAMETER NAME="PCW_EN_DDR" VALUE="1"/>
        <PARAMETER NAME="PCW_EN_SMC" VALUE="0"/>
        <PARAMETER NAME="PCW_EN_QSPI" VALUE="0"/>
        <PARAMETER NAME="PCW_EN_CAN0" VALUE="0"/>
        <PARAMETER NAME="PCW_EN_CAN1" VALUE="0"/>
        <PARAMETER NAME="PCW_EN_ENET0" VALUE="1"/>
        <PARAMETER NAME="PCW_EN_ENET1" VALUE="0"/>
        <PARAMETER NAME="PCW_EN_GPIO" VALUE="1"/>
        <PARAMETER NAME="PCW_EN_I2C0" VALUE="1"/>
        <PARAMETER NAME="PCW_EN_I2C1" VALUE="0"/>
        <PARAMETER NAME="PCW_EN_PJTAG" VALUE="0"/>
        <PARAMETER NAME="PCW_EN_SDIO0" VALUE="1"/>
        <PARAMETER NAME="PCW_EN_SDIO1" VALUE="0"/>
        <PARAMETER NAME="PCW_EN_SPI0" VALUE="1"/>
        <PARAMETER NAME="PCW_EN_SPI1" VALUE="1"/>
        <PARAMETER NAME="PCW_EN_UART0" VALUE="1"/>
        <PARAMETER NAME="PCW_EN_UART1" VALUE="1"/>
        <PARAMETER NAME="PCW_EN_MODEM_UART0" VALUE="0"/>
        <PARAMETER NAME="PCW_EN_MODEM_UART1" VALUE="0"/>
        <PARAMETER NAME="PCW_EN_TTC0" VALUE="0"/>
        <PARAMETER NAME="PCW_EN_TTC1" VALUE="0"/>
        <PARAMETER NAME="PCW_EN_WDT" VALUE="0"/>
        <PARAMETER NAME="PCW_EN_TRACE" VALUE="0"/>
        <PARAMETER NAME="PCW_EN_USB0" VALUE="1"/>
        <PARAMETER NAME="PCW_EN_USB1" VALUE="0"/>
        <PARAMETER NAME="PCW_DQ_WIDTH" VALUE="32"/>
        <PARAMETER NAME="PCW_DQS_WIDTH" VALUE="4"/>
        <PARAMETER NAME="PCW_DM_WIDTH" VALUE="4"/>
        <PARAMETER NAME="PCW_MIO_PRIMITIVE" VALUE="54"/>
        <PARAMETER NAME="PCW_EN_CLK0_PORT" VALUE="1"/>
        <PARAMETER NAME="PCW_EN_CLK1_PORT" VALUE="0"/>
        <PARAMETER NAME="PCW_EN_CLK2_PORT" VALUE="0"/>
        <PARAMETER NAME="PCW_EN_CLK3_PORT" VALUE="0"/>
        <PARAMETER NAME="PCW_EN_RST0_PORT" VALUE="1"/>
        <PARAMETER NAME="PCW_EN_RST1_PORT" VALUE="0"/>
        <PARAMETER NAME="PCW_EN_RST2_PORT" VALUE="0"/>
        <PARAMETER NAME="PCW_EN_RST3_PORT" VALUE="0"/>
        <PARAMETER NAME="PCW_EN_CLKTRIG0_PORT" VALUE="0"/>
        <PARAMETER NAME="PCW_EN_CLKTRIG1_PORT" VALUE="0"/>
        <PARAMETER NAME="PCW_EN_CLKTRIG2_PORT" VALUE="0"/>
        <PARAMETER NAME="PCW_EN_CLKTRIG3_PORT" VALUE="0"/>
        <PARAMETER NAME="PCW_P2F_DMAC_ABORT_INTR" VALUE="0"/>
        <PARAMETER NAME="PCW_P2F_DMAC0_INTR" VALUE="0"/>
        <PARAMETER NAME="PCW_P2F_DMAC1_INTR" VALUE="0"/>
        <PARAMETER NAME="PCW_P2F_DMAC2_INTR" VALUE="0"/>
        <PARAMETER NAME="PCW_P2F_DMAC3_INTR" VALUE="0"/>
        <PARAMETER NAME="PCW_P2F_DMAC4_INTR" VALUE="0"/>
        <PARAMETER NAME="PCW_P2F_DMAC5_INTR" VALUE="0"/>
        <PARAMETER NAME="PCW_P2F_DMAC6_INTR" VALUE="0"/>
        <PARAMETER NAME="PCW_P2F_DMAC7_INTR" VALUE="0"/>
        <PARAMETER NAME="PCW_P2F_SMC_INTR" VALUE="0"/>
        <PARAMETER NAME="PCW_P2F_QSPI_INTR" VALUE="0"/>
        <PARAMETER NAME="PCW_P2F_CTI_INTR" VALUE="0"/>
        <PARAMETER NAME="PCW_P2F_GPIO_INTR" VALUE="0"/>
        <PARAMETER NAME="PCW_P2F_USB0_INTR" VALUE="0"/>
        <PARAMETER NAME="PCW_P2F_ENET0_INTR" VALUE="0"/>
        <PARAMETER NAME="PCW_P2F_SDIO0_INTR" VALUE="0"/>
        <PARAMETER NAME="PCW_P2F_I2C0_INTR" VALUE="0"/>
        <PARAMETER NAME="PCW_P2F_SPI0_INTR" VALUE="0"/>
        <PARAMETER NAME="PCW_P2F_UART0_INTR" VALUE="0"/>
        <PARAMETER NAME="PCW_P2F_CAN0_INTR" VALUE="0"/>
        <PARAMETER NAME="PCW_P2F_USB1_INTR" VALUE="0"/>
        <PARAMETER NAME="PCW_P2F_ENET1_INTR" VALUE="0"/>
        <PARAMETER NAME="PCW_P2F_SDIO1_INTR" VALUE="0"/>
        <PARAMETER NAME="PCW_P2F_I2C1_INTR" VALUE="0"/>
        <PARAMETER NAME="PCW_P2F_SPI1_INTR" VALUE="0"/>
        <PARAMETER NAME="PCW_P2F_UART1_INTR" VALUE="0"/>
        <PARAMETER NAME="PCW_P2F_CAN1_INTR" VALUE="0"/>
        <PARAMETER NAME="PCW_IRQ_F2P_INTR" VALUE="0"/>
        <PARAMETER NAME="PCW_IRQ_F2P_MODE" VALUE="DIRECT"/>
        <PARAMETER NAME="PCW_CORE0_FIQ_INTR" VALUE="0"/>
        <PARAMETER NAME="PCW_CORE0_IRQ_INTR" VALUE="0"/>
        <PARAMETER NAME="PCW_CORE1_FIQ_INTR" VALUE="0"/>
        <PARAMETER NAME="PCW_CORE1_IRQ_INTR" VALUE="0"/>
        <PARAMETER NAME="PCW_VALUE_SILVERSION" VALUE="3"/>
        <PARAMETER NAME="PCW_GP0_EN_MODIFIABLE_TXN" VALUE="1"/>
        <PARAMETER NAME="PCW_GP1_EN_MODIFIABLE_TXN" VALUE="1"/>
        <PARAMETER NAME="PCW_IMPORT_BOARD_PRESET" VALUE="cfg/red_pitaya.xml"/>
        <PARAMETER NAME="PCW_PERIPHERAL_BOARD_PRESET" VALUE="None"/>
        <PARAMETER NAME="PCW_PRESET_BANK0_VOLTAGE" VALUE="LVCMOS 3.3V"/>
        <PARAMETER NAME="PCW_PRESET_BANK1_VOLTAGE" VALUE="LVCMOS 2.5V"/>
        <PARAMETER NAME="PCW_UIPARAM_DDR_ENABLE" VALUE="1"/>
        <PARAMETER NAME="PCW_UIPARAM_DDR_ADV_ENABLE" VALUE="0"/>
        <PARAMETER NAME="PCW_UIPARAM_DDR_MEMORY_TYPE" VALUE="DDR 3"/>
        <PARAMETER NAME="PCW_UIPARAM_DDR_ECC" VALUE="Disabled"/>
        <PARAMETER NAME="PCW_UIPARAM_DDR_BUS_WIDTH" VALUE="16 Bit"/>
        <PARAMETER NAME="PCW_UIPARAM_DDR_BL" VALUE="8"/>
        <PARAMETER NAME="PCW_UIPARAM_DDR_HIGH_TEMP" VALUE="Normal (0-85)"/>
        <PARAMETER NAME="PCW_UIPARAM_DDR_PARTNO" VALUE="MT41J256M16 RE-125"/>
        <PARAMETER NAME="PCW_UIPARAM_DDR_DRAM_WIDTH" VALUE="16 Bits"/>
        <PARAMETER NAME="PCW_UIPARAM_DDR_DEVICE_CAPACITY" VALUE="4096 MBits"/>
        <PARAMETER NAME="PCW_UIPARAM_DDR_SPEED_BIN" VALUE="DDR3_1066F"/>
        <PARAMETER NAME="PCW_UIPARAM_DDR_TRAIN_WRITE_LEVEL" VALUE="1"/>
        <PARAMETER NAME="PCW_UIPARAM_DDR_TRAIN_READ_GATE" VALUE="1"/>
        <PARAMETER NAME="PCW_UIPARAM_DDR_TRAIN_DATA_EYE" VALUE="1"/>
        <PARAMETER NAME="PCW_UIPARAM_DDR_CLOCK_STOP_EN" VALUE="0"/>
        <PARAMETER NAME="PCW_UIPARAM_DDR_USE_INTERNAL_VREF" VALUE="0"/>
        <PARAMETER NAME="PCW_DDR_PRIORITY_WRITEPORT_0" VALUE="&lt;Select>"/>
        <PARAMETER NAME="PCW_DDR_PRIORITY_WRITEPORT_1" VALUE="&lt;Select>"/>
        <PARAMETER NAME="PCW_DDR_PRIORITY_WRITEPORT_2" VALUE="&lt;Select>"/>
        <PARAMETER NAME="PCW_DDR_PRIORITY_WRITEPORT_3" VALUE="&lt;Select>"/>
        <PARAMETER NAME="PCW_DDR_PRIORITY_READPORT_0" VALUE="&lt;Select>"/>
        <PARAMETER NAME="PCW_DDR_PRIORITY_READPORT_1" VALUE="&lt;Select>"/>
        <PARAMETER NAME="PCW_DDR_PRIORITY_READPORT_2" VALUE="&lt;Select>"/>
        <PARAMETER NAME="PCW_DDR_PRIORITY_READPORT_3" VALUE="&lt;Select>"/>
        <PARAMETER NAME="PCW_DDR_PORT0_HPR_ENABLE" VALUE="0"/>
        <PARAMETER NAME="PCW_DDR_PORT1_HPR_ENABLE" VALUE="0"/>
        <PARAMETER NAME="PCW_DDR_PORT2_HPR_ENABLE" VALUE="0"/>
        <PARAMETER NAME="PCW_DDR_PORT3_HPR_ENABLE" VALUE="0"/>
        <PARAMETER NAME="PCW_DDR_HPRLPR_QUEUE_PARTITION" VALUE="HPR(0)/LPR(32)"/>
        <PARAMETER NAME="PCW_DDR_LPR_TO_CRITICAL_PRIORITY_LEVEL" VALUE="2"/>
        <PARAMETER NAME="PCW_DDR_HPR_TO_CRITICAL_PRIORITY_LEVEL" VALUE="15"/>
        <PARAMETER NAME="PCW_DDR_WRITE_TO_CRITICAL_PRIORITY_LEVEL" VALUE="2"/>
        <PARAMETER NAME="PCW_NAND_PERIPHERAL_ENABLE" VALUE="0"/>
        <PARAMETER NAME="PCW_NAND_NAND_IO" VALUE="&lt;Select>"/>
        <PARAMETER NAME="PCW_NAND_GRP_D8_ENABLE" VALUE="0"/>
        <PARAMETER NAME="PCW_NAND_GRP_D8_IO" VALUE="&lt;Select>"/>
        <PARAMETER NAME="PCW_NOR_PERIPHERAL_ENABLE" VALUE="0"/>
        <PARAMETER NAME="PCW_NOR_NOR_IO" VALUE="&lt;Select>"/>
        <PARAMETER NAME="PCW_NOR_GRP_A25_ENABLE" VALUE="0"/>
        <PARAMETER NAME="PCW_NOR_GRP_A25_IO" VALUE="&lt;Select>"/>
        <PARAMETER NAME="PCW_NOR_GRP_CS0_ENABLE" VALUE="0"/>
        <PARAMETER NAME="PCW_NOR_GRP_CS0_IO" VALUE="&lt;Select>"/>
        <PARAMETER NAME="PCW_NOR_GRP_SRAM_CS0_ENABLE" VALUE="0"/>
        <PARAMETER NAME="PCW_NOR_GRP_SRAM_CS0_IO" VALUE="&lt;Select>"/>
        <PARAMETER NAME="PCW_NOR_GRP_CS1_ENABLE" VALUE="0"/>
        <PARAMETER NAME="PCW_NOR_GRP_CS1_IO" VALUE="&lt;Select>"/>
        <PARAMETER NAME="PCW_NOR_GRP_SRAM_CS1_ENABLE" VALUE="0"/>
        <PARAMETER NAME="PCW_NOR_GRP_SRAM_CS1_IO" VALUE="&lt;Select>"/>
        <PARAMETER NAME="PCW_NOR_GRP_SRAM_INT_ENABLE" VALUE="0"/>
        <PARAMETER NAME="PCW_NOR_GRP_SRAM_INT_IO" VALUE="&lt;Select>"/>
        <PARAMETER NAME="PCW_QSPI_PERIPHERAL_ENABLE" VALUE="0"/>
        <PARAMETER NAME="PCW_QSPI_QSPI_IO" VALUE="&lt;Select>"/>
        <PARAMETER NAME="PCW_QSPI_GRP_SINGLE_SS_ENABLE" VALUE="0"/>
        <PARAMETER NAME="PCW_QSPI_GRP_SINGLE_SS_IO" VALUE="&lt;Select>"/>
        <PARAMETER NAME="PCW_QSPI_GRP_SS1_ENABLE" VALUE="0"/>
        <PARAMETER NAME="PCW_QSPI_GRP_SS1_IO" VALUE="&lt;Select>"/>
        <PARAMETER NAME="PCW_SINGLE_QSPI_DATA_MODE" VALUE="&lt;Select>"/>
        <PARAMETER NAME="PCW_DUAL_STACK_QSPI_DATA_MODE" VALUE="&lt;Select>"/>
        <PARAMETER NAME="PCW_DUAL_PARALLEL_QSPI_DATA_MODE" VALUE="&lt;Select>"/>
        <PARAMETER NAME="PCW_QSPI_GRP_IO1_ENABLE" VALUE="0"/>
        <PARAMETER NAME="PCW_QSPI_GRP_IO1_IO" VALUE="&lt;Select>"/>
        <PARAMETER NAME="PCW_QSPI_GRP_FBCLK_ENABLE" VALUE="0"/>
        <PARAMETER NAME="PCW_QSPI_GRP_FBCLK_IO" VALUE="&lt;Select>"/>
        <PARAMETER NAME="PCW_QSPI_INTERNAL_HIGHADDRESS" VALUE="0xFCFFFFFF"/>
        <PARAMETER NAME="PCW_ENET0_PERIPHERAL_ENABLE" VALUE="1"/>
        <PARAMETER NAME="PCW_ENET0_ENET0_IO" VALUE="MIO 16 .. 27"/>
        <PARAMETER NAME="PCW_ENET0_GRP_MDIO_ENABLE" VALUE="1"/>
        <PARAMETER NAME="PCW_ENET0_GRP_MDIO_IO" VALUE="MIO 52 .. 53"/>
        <PARAMETER NAME="PCW_ENET_RESET_ENABLE" VALUE="1"/>
        <PARAMETER NAME="PCW_ENET_RESET_SELECT" VALUE="Share reset pin"/>
        <PARAMETER NAME="PCW_ENET0_RESET_ENABLE" VALUE="0"/>
        <PARAMETER NAME="PCW_ENET0_RESET_IO" VALUE="&lt;Select>"/>
        <PARAMETER NAME="PCW_ENET1_PERIPHERAL_ENABLE" VALUE="0"/>
        <PARAMETER NAME="PCW_ENET1_ENET1_IO" VALUE="&lt;Select>"/>
        <PARAMETER NAME="PCW_ENET1_GRP_MDIO_ENABLE" VALUE="0"/>
        <PARAMETER NAME="PCW_ENET1_GRP_MDIO_IO" VALUE="&lt;Select>"/>
        <PARAMETER NAME="PCW_ENET1_RESET_ENABLE" VALUE="0"/>
        <PARAMETER NAME="PCW_ENET1_RESET_IO" VALUE="&lt;Select>"/>
        <PARAMETER NAME="PCW_SD0_PERIPHERAL_ENABLE" VALUE="1"/>
        <PARAMETER NAME="PCW_SD0_SD0_IO" VALUE="MIO 40 .. 45"/>
        <PARAMETER NAME="PCW_SD0_GRP_CD_ENABLE" VALUE="1"/>
        <PARAMETER NAME="PCW_SD0_GRP_CD_IO" VALUE="MIO 46"/>
        <PARAMETER NAME="PCW_SD0_GRP_WP_ENABLE" VALUE="1"/>
        <PARAMETER NAME="PCW_SD0_GRP_WP_IO" VALUE="MIO 47"/>
        <PARAMETER NAME="PCW_SD0_GRP_POW_ENABLE" VALUE="0"/>
        <PARAMETER NAME="PCW_SD0_GRP_POW_IO" VALUE="&lt;Select>"/>
        <PARAMETER NAME="PCW_SD1_PERIPHERAL_ENABLE" VALUE="0"/>
        <PARAMETER NAME="PCW_SD1_SD1_IO" VALUE="&lt;Select>"/>
        <PARAMETER NAME="PCW_SD1_GRP_CD_ENABLE" VALUE="0"/>
        <PARAMETER NAME="PCW_SD1_GRP_CD_IO" VALUE="&lt;Select>"/>
        <PARAMETER NAME="PCW_SD1_GRP_WP_ENABLE" VALUE="0"/>
        <PARAMETER NAME="PCW_SD1_GRP_WP_IO" VALUE="&lt;Select>"/>
        <PARAMETER NAME="PCW_SD1_GRP_POW_ENABLE" VALUE="0"/>
        <PARAMETER NAME="PCW_SD1_GRP_POW_IO" VALUE="&lt;Select>"/>
        <PARAMETER NAME="PCW_UART0_PERIPHERAL_ENABLE" VALUE="1"/>
        <PARAMETER NAME="PCW_UART0_UART0_IO" VALUE="MIO 14 .. 15"/>
        <PARAMETER NAME="PCW_UART0_GRP_FULL_ENABLE" VALUE="0"/>
        <PARAMETER NAME="PCW_UART0_GRP_FULL_IO" VALUE="&lt;Select>"/>
        <PARAMETER NAME="PCW_UART1_PERIPHERAL_ENABLE" VALUE="1"/>
        <PARAMETER NAME="PCW_UART1_UART1_IO" VALUE="MIO 8 .. 9"/>
        <PARAMETER NAME="PCW_UART1_GRP_FULL_ENABLE" VALUE="0"/>
        <PARAMETER NAME="PCW_UART1_GRP_FULL_IO" VALUE="&lt;Select>"/>
        <PARAMETER NAME="PCW_SPI0_PERIPHERAL_ENABLE" VALUE="1"/>
        <PARAMETER NAME="PCW_SPI0_SPI0_IO" VALUE="EMIO"/>
        <PARAMETER NAME="PCW_SPI0_GRP_SS0_ENABLE" VALUE="1"/>
        <PARAMETER NAME="PCW_SPI0_GRP_SS0_IO" VALUE="EMIO"/>
        <PARAMETER NAME="PCW_SPI0_GRP_SS1_ENABLE" VALUE="1"/>
        <PARAMETER NAME="PCW_SPI0_GRP_SS1_IO" VALUE="EMIO"/>
        <PARAMETER NAME="PCW_SPI0_GRP_SS2_ENABLE" VALUE="1"/>
        <PARAMETER NAME="PCW_SPI0_GRP_SS2_IO" VALUE="EMIO"/>
        <PARAMETER NAME="PCW_SPI1_PERIPHERAL_ENABLE" VALUE="1"/>
        <PARAMETER NAME="PCW_SPI1_SPI1_IO" VALUE="MIO 10 .. 15"/>
        <PARAMETER NAME="PCW_SPI1_GRP_SS0_ENABLE" VALUE="1"/>
        <PARAMETER NAME="PCW_SPI1_GRP_SS0_IO" VALUE="MIO 13"/>
        <PARAMETER NAME="PCW_SPI1_GRP_SS1_ENABLE" VALUE="0"/>
        <PARAMETER NAME="PCW_SPI1_GRP_SS1_IO" VALUE="&lt;Select>"/>
        <PARAMETER NAME="PCW_SPI1_GRP_SS2_ENABLE" VALUE="0"/>
        <PARAMETER NAME="PCW_SPI1_GRP_SS2_IO" VALUE="&lt;Select>"/>
        <PARAMETER NAME="PCW_CAN0_PERIPHERAL_ENABLE" VALUE="0"/>
        <PARAMETER NAME="PCW_CAN0_CAN0_IO" VALUE="&lt;Select>"/>
        <PARAMETER NAME="PCW_CAN0_GRP_CLK_ENABLE" VALUE="0"/>
        <PARAMETER NAME="PCW_CAN0_GRP_CLK_IO" VALUE="&lt;Select>"/>
        <PARAMETER NAME="PCW_CAN1_PERIPHERAL_ENABLE" VALUE="0"/>
        <PARAMETER NAME="PCW_CAN1_CAN1_IO" VALUE="&lt;Select>"/>
        <PARAMETER NAME="PCW_CAN1_GRP_CLK_ENABLE" VALUE="0"/>
        <PARAMETER NAME="PCW_CAN1_GRP_CLK_IO" VALUE="&lt;Select>"/>
        <PARAMETER NAME="PCW_TRACE_PERIPHERAL_ENABLE" VALUE="0"/>
        <PARAMETER NAME="PCW_TRACE_TRACE_IO" VALUE="&lt;Select>"/>
        <PARAMETER NAME="PCW_TRACE_GRP_2BIT_ENABLE" VALUE="0"/>
        <PARAMETER NAME="PCW_TRACE_GRP_2BIT_IO" VALUE="&lt;Select>"/>
        <PARAMETER NAME="PCW_TRACE_GRP_4BIT_ENABLE" VALUE="0"/>
        <PARAMETER NAME="PCW_TRACE_GRP_4BIT_IO" VALUE="&lt;Select>"/>
        <PARAMETER NAME="PCW_TRACE_GRP_8BIT_ENABLE" VALUE="0"/>
        <PARAMETER NAME="PCW_TRACE_GRP_8BIT_IO" VALUE="&lt;Select>"/>
        <PARAMETER NAME="PCW_TRACE_GRP_16BIT_ENABLE" VALUE="0"/>
        <PARAMETER NAME="PCW_TRACE_GRP_16BIT_IO" VALUE="&lt;Select>"/>
        <PARAMETER NAME="PCW_TRACE_GRP_32BIT_ENABLE" VALUE="0"/>
        <PARAMETER NAME="PCW_TRACE_GRP_32BIT_IO" VALUE="&lt;Select>"/>
        <PARAMETER NAME="PCW_TRACE_INTERNAL_WIDTH" VALUE="2"/>
        <PARAMETER NAME="PCW_WDT_PERIPHERAL_ENABLE" VALUE="0"/>
        <PARAMETER NAME="PCW_WDT_WDT_IO" VALUE="&lt;Select>"/>
        <PARAMETER NAME="PCW_TTC0_PERIPHERAL_ENABLE" VALUE="0"/>
        <PARAMETER NAME="PCW_TTC0_TTC0_IO" VALUE="&lt;Select>"/>
        <PARAMETER NAME="PCW_TTC1_PERIPHERAL_ENABLE" VALUE="0"/>
        <PARAMETER NAME="PCW_TTC1_TTC1_IO" VALUE="&lt;Select>"/>
        <PARAMETER NAME="PCW_PJTAG_PERIPHERAL_ENABLE" VALUE="0"/>
        <PARAMETER NAME="PCW_PJTAG_PJTAG_IO" VALUE="&lt;Select>"/>
        <PARAMETER NAME="PCW_USB0_PERIPHERAL_ENABLE" VALUE="1"/>
        <PARAMETER NAME="PCW_USB0_USB0_IO" VALUE="MIO 28 .. 39"/>
        <PARAMETER NAME="PCW_USB_RESET_ENABLE" VALUE="1"/>
        <PARAMETER NAME="PCW_USB_RESET_SELECT" VALUE="Share reset pin"/>
        <PARAMETER NAME="PCW_USB0_RESET_ENABLE" VALUE="1"/>
        <PARAMETER NAME="PCW_USB0_RESET_IO" VALUE="MIO 48"/>
        <PARAMETER NAME="PCW_USB1_PERIPHERAL_ENABLE" VALUE="0"/>
        <PARAMETER NAME="PCW_USB1_USB1_IO" VALUE="&lt;Select>"/>
        <PARAMETER NAME="PCW_USB1_RESET_ENABLE" VALUE="0"/>
        <PARAMETER NAME="PCW_USB1_RESET_IO" VALUE="&lt;Select>"/>
        <PARAMETER NAME="PCW_I2C0_PERIPHERAL_ENABLE" VALUE="1"/>
        <PARAMETER NAME="PCW_I2C0_I2C0_IO" VALUE="MIO 50 .. 51"/>
        <PARAMETER NAME="PCW_I2C0_GRP_INT_ENABLE" VALUE="0"/>
        <PARAMETER NAME="PCW_I2C0_GRP_INT_IO" VALUE="&lt;Select>"/>
        <PARAMETER NAME="PCW_I2C0_RESET_ENABLE" VALUE="0"/>
        <PARAMETER NAME="PCW_I2C0_RESET_IO" VALUE="&lt;Select>"/>
        <PARAMETER NAME="PCW_I2C1_PERIPHERAL_ENABLE" VALUE="0"/>
        <PARAMETER NAME="PCW_I2C1_I2C1_IO" VALUE="&lt;Select>"/>
        <PARAMETER NAME="PCW_I2C1_GRP_INT_ENABLE" VALUE="0"/>
        <PARAMETER NAME="PCW_I2C1_GRP_INT_IO" VALUE="&lt;Select>"/>
        <PARAMETER NAME="PCW_I2C_RESET_ENABLE" VALUE="1"/>
        <PARAMETER NAME="PCW_I2C_RESET_SELECT" VALUE="Share reset pin"/>
        <PARAMETER NAME="PCW_I2C1_RESET_ENABLE" VALUE="0"/>
        <PARAMETER NAME="PCW_I2C1_RESET_IO" VALUE="&lt;Select>"/>
        <PARAMETER NAME="PCW_GPIO_PERIPHERAL_ENABLE" VALUE="1"/>
        <PARAMETER NAME="PCW_GPIO_MIO_GPIO_ENABLE" VALUE="1"/>
        <PARAMETER NAME="PCW_GPIO_MIO_GPIO_IO" VALUE="MIO"/>
        <PARAMETER NAME="PCW_GPIO_EMIO_GPIO_ENABLE" VALUE="1"/>
        <PARAMETER NAME="PCW_GPIO_EMIO_GPIO_IO" VALUE="64"/>
        <PARAMETER NAME="PCW_APU_CLK_RATIO_ENABLE" VALUE="6:2:1"/>
        <PARAMETER NAME="PCW_ENET0_PERIPHERAL_FREQMHZ" VALUE="1000 Mbps"/>
        <PARAMETER NAME="PCW_ENET1_PERIPHERAL_FREQMHZ" VALUE="1000 Mbps"/>
        <PARAMETER NAME="PCW_CPU_PERIPHERAL_CLKSRC" VALUE="ARM PLL"/>
        <PARAMETER NAME="PCW_DDR_PERIPHERAL_CLKSRC" VALUE="DDR PLL"/>
        <PARAMETER NAME="PCW_SMC_PERIPHERAL_CLKSRC" VALUE="IO PLL"/>
        <PARAMETER NAME="PCW_QSPI_PERIPHERAL_CLKSRC" VALUE="IO PLL"/>
        <PARAMETER NAME="PCW_SDIO_PERIPHERAL_CLKSRC" VALUE="IO PLL"/>
        <PARAMETER NAME="PCW_UART_PERIPHERAL_CLKSRC" VALUE="IO PLL"/>
        <PARAMETER NAME="PCW_SPI_PERIPHERAL_CLKSRC" VALUE="IO PLL"/>
        <PARAMETER NAME="PCW_CAN_PERIPHERAL_CLKSRC" VALUE="IO PLL"/>
        <PARAMETER NAME="PCW_FCLK0_PERIPHERAL_CLKSRC" VALUE="IO PLL"/>
        <PARAMETER NAME="PCW_FCLK1_PERIPHERAL_CLKSRC" VALUE="IO PLL"/>
        <PARAMETER NAME="PCW_FCLK2_PERIPHERAL_CLKSRC" VALUE="IO PLL"/>
        <PARAMETER NAME="PCW_FCLK3_PERIPHERAL_CLKSRC" VALUE="IO PLL"/>
        <PARAMETER NAME="PCW_ENET0_PERIPHERAL_CLKSRC" VALUE="IO PLL"/>
        <PARAMETER NAME="PCW_ENET1_PERIPHERAL_CLKSRC" VALUE="IO PLL"/>
        <PARAMETER NAME="PCW_CAN0_PERIPHERAL_CLKSRC" VALUE="External"/>
        <PARAMETER NAME="PCW_CAN1_PERIPHERAL_CLKSRC" VALUE="External"/>
        <PARAMETER NAME="PCW_TPIU_PERIPHERAL_CLKSRC" VALUE="External"/>
        <PARAMETER NAME="PCW_TTC0_CLK0_PERIPHERAL_CLKSRC" VALUE="CPU_1X"/>
        <PARAMETER NAME="PCW_TTC0_CLK1_PERIPHERAL_CLKSRC" VALUE="CPU_1X"/>
        <PARAMETER NAME="PCW_TTC0_CLK2_PERIPHERAL_CLKSRC" VALUE="CPU_1X"/>
        <PARAMETER NAME="PCW_TTC1_CLK0_PERIPHERAL_CLKSRC" VALUE="CPU_1X"/>
        <PARAMETER NAME="PCW_TTC1_CLK1_PERIPHERAL_CLKSRC" VALUE="CPU_1X"/>
        <PARAMETER NAME="PCW_TTC1_CLK2_PERIPHERAL_CLKSRC" VALUE="CPU_1X"/>
        <PARAMETER NAME="PCW_WDT_PERIPHERAL_CLKSRC" VALUE="CPU_1X"/>
        <PARAMETER NAME="PCW_DCI_PERIPHERAL_CLKSRC" VALUE="DDR PLL"/>
        <PARAMETER NAME="PCW_PCAP_PERIPHERAL_CLKSRC" VALUE="IO PLL"/>
        <PARAMETER NAME="PCW_USB_RESET_POLARITY" VALUE="Active Low"/>
        <PARAMETER NAME="PCW_ENET_RESET_POLARITY" VALUE="Active Low"/>
        <PARAMETER NAME="PCW_I2C_RESET_POLARITY" VALUE="Active Low"/>
        <PARAMETER NAME="PCW_MIO_0_PULLUP" VALUE="disabled"/>
        <PARAMETER NAME="PCW_MIO_0_IOTYPE" VALUE="LVCMOS 3.3V"/>
        <PARAMETER NAME="PCW_MIO_0_DIRECTION" VALUE="inout"/>
        <PARAMETER NAME="PCW_MIO_0_SLEW" VALUE="slow"/>
        <PARAMETER NAME="PCW_MIO_1_PULLUP" VALUE="enabled"/>
        <PARAMETER NAME="PCW_MIO_1_IOTYPE" VALUE="LVCMOS 3.3V"/>
        <PARAMETER NAME="PCW_MIO_1_DIRECTION" VALUE="inout"/>
        <PARAMETER NAME="PCW_MIO_1_SLEW" VALUE="slow"/>
        <PARAMETER NAME="PCW_MIO_2_PULLUP" VALUE="disabled"/>
        <PARAMETER NAME="PCW_MIO_2_IOTYPE" VALUE="LVCMOS 3.3V"/>
        <PARAMETER NAME="PCW_MIO_2_DIRECTION" VALUE="inout"/>
        <PARAMETER NAME="PCW_MIO_2_SLEW" VALUE="slow"/>
        <PARAMETER NAME="PCW_MIO_3_PULLUP" VALUE="disabled"/>
        <PARAMETER NAME="PCW_MIO_3_IOTYPE" VALUE="LVCMOS 3.3V"/>
        <PARAMETER NAME="PCW_MIO_3_DIRECTION" VALUE="inout"/>
        <PARAMETER NAME="PCW_MIO_3_SLEW" VALUE="slow"/>
        <PARAMETER NAME="PCW_MIO_4_PULLUP" VALUE="disabled"/>
        <PARAMETER NAME="PCW_MIO_4_IOTYPE" VALUE="LVCMOS 3.3V"/>
        <PARAMETER NAME="PCW_MIO_4_DIRECTION" VALUE="inout"/>
        <PARAMETER NAME="PCW_MIO_4_SLEW" VALUE="slow"/>
        <PARAMETER NAME="PCW_MIO_5_PULLUP" VALUE="disabled"/>
        <PARAMETER NAME="PCW_MIO_5_IOTYPE" VALUE="LVCMOS 3.3V"/>
        <PARAMETER NAME="PCW_MIO_5_DIRECTION" VALUE="inout"/>
        <PARAMETER NAME="PCW_MIO_5_SLEW" VALUE="slow"/>
        <PARAMETER NAME="PCW_MIO_6_PULLUP" VALUE="disabled"/>
        <PARAMETER NAME="PCW_MIO_6_IOTYPE" VALUE="LVCMOS 3.3V"/>
        <PARAMETER NAME="PCW_MIO_6_DIRECTION" VALUE="inout"/>
        <PARAMETER NAME="PCW_MIO_6_SLEW" VALUE="slow"/>
        <PARAMETER NAME="PCW_MIO_7_PULLUP" VALUE="disabled"/>
        <PARAMETER NAME="PCW_MIO_7_IOTYPE" VALUE="LVCMOS 3.3V"/>
        <PARAMETER NAME="PCW_MIO_7_DIRECTION" VALUE="out"/>
        <PARAMETER NAME="PCW_MIO_7_SLEW" VALUE="slow"/>
        <PARAMETER NAME="PCW_MIO_8_PULLUP" VALUE="disabled"/>
        <PARAMETER NAME="PCW_MIO_8_IOTYPE" VALUE="LVCMOS 3.3V"/>
        <PARAMETER NAME="PCW_MIO_8_DIRECTION" VALUE="out"/>
        <PARAMETER NAME="PCW_MIO_8_SLEW" VALUE="slow"/>
        <PARAMETER NAME="PCW_MIO_9_PULLUP" VALUE="enabled"/>
        <PARAMETER NAME="PCW_MIO_9_IOTYPE" VALUE="LVCMOS 3.3V"/>
        <PARAMETER NAME="PCW_MIO_9_DIRECTION" VALUE="in"/>
        <PARAMETER NAME="PCW_MIO_9_SLEW" VALUE="slow"/>
        <PARAMETER NAME="PCW_MIO_10_PULLUP" VALUE="enabled"/>
        <PARAMETER NAME="PCW_MIO_10_IOTYPE" VALUE="LVCMOS 3.3V"/>
        <PARAMETER NAME="PCW_MIO_10_DIRECTION" VALUE="inout"/>
        <PARAMETER NAME="PCW_MIO_10_SLEW" VALUE="slow"/>
        <PARAMETER NAME="PCW_MIO_11_PULLUP" VALUE="enabled"/>
        <PARAMETER NAME="PCW_MIO_11_IOTYPE" VALUE="LVCMOS 3.3V"/>
        <PARAMETER NAME="PCW_MIO_11_DIRECTION" VALUE="inout"/>
        <PARAMETER NAME="PCW_MIO_11_SLEW" VALUE="slow"/>
        <PARAMETER NAME="PCW_MIO_12_PULLUP" VALUE="enabled"/>
        <PARAMETER NAME="PCW_MIO_12_IOTYPE" VALUE="LVCMOS 3.3V"/>
        <PARAMETER NAME="PCW_MIO_12_DIRECTION" VALUE="inout"/>
        <PARAMETER NAME="PCW_MIO_12_SLEW" VALUE="slow"/>
        <PARAMETER NAME="PCW_MIO_13_PULLUP" VALUE="enabled"/>
        <PARAMETER NAME="PCW_MIO_13_IOTYPE" VALUE="LVCMOS 3.3V"/>
        <PARAMETER NAME="PCW_MIO_13_DIRECTION" VALUE="inout"/>
        <PARAMETER NAME="PCW_MIO_13_SLEW" VALUE="slow"/>
        <PARAMETER NAME="PCW_MIO_14_PULLUP" VALUE="enabled"/>
        <PARAMETER NAME="PCW_MIO_14_IOTYPE" VALUE="LVCMOS 3.3V"/>
        <PARAMETER NAME="PCW_MIO_14_DIRECTION" VALUE="in"/>
        <PARAMETER NAME="PCW_MIO_14_SLEW" VALUE="slow"/>
        <PARAMETER NAME="PCW_MIO_15_PULLUP" VALUE="enabled"/>
        <PARAMETER NAME="PCW_MIO_15_IOTYPE" VALUE="LVCMOS 3.3V"/>
        <PARAMETER NAME="PCW_MIO_15_DIRECTION" VALUE="out"/>
        <PARAMETER NAME="PCW_MIO_15_SLEW" VALUE="slow"/>
        <PARAMETER NAME="PCW_MIO_16_PULLUP" VALUE="disabled"/>
        <PARAMETER NAME="PCW_MIO_16_IOTYPE" VALUE="LVCMOS 2.5V"/>
        <PARAMETER NAME="PCW_MIO_16_DIRECTION" VALUE="out"/>
        <PARAMETER NAME="PCW_MIO_16_SLEW" VALUE="fast"/>
        <PARAMETER NAME="PCW_MIO_17_PULLUP" VALUE="disabled"/>
        <PARAMETER NAME="PCW_MIO_17_IOTYPE" VALUE="LVCMOS 2.5V"/>
        <PARAMETER NAME="PCW_MIO_17_DIRECTION" VALUE="out"/>
        <PARAMETER NAME="PCW_MIO_17_SLEW" VALUE="fast"/>
        <PARAMETER NAME="PCW_MIO_18_PULLUP" VALUE="disabled"/>
        <PARAMETER NAME="PCW_MIO_18_IOTYPE" VALUE="LVCMOS 2.5V"/>
        <PARAMETER NAME="PCW_MIO_18_DIRECTION" VALUE="out"/>
        <PARAMETER NAME="PCW_MIO_18_SLEW" VALUE="fast"/>
        <PARAMETER NAME="PCW_MIO_19_PULLUP" VALUE="disabled"/>
        <PARAMETER NAME="PCW_MIO_19_IOTYPE" VALUE="LVCMOS 2.5V"/>
        <PARAMETER NAME="PCW_MIO_19_DIRECTION" VALUE="out"/>
        <PARAMETER NAME="PCW_MIO_19_SLEW" VALUE="fast"/>
        <PARAMETER NAME="PCW_MIO_20_PULLUP" VALUE="disabled"/>
        <PARAMETER NAME="PCW_MIO_20_IOTYPE" VALUE="LVCMOS 2.5V"/>
        <PARAMETER NAME="PCW_MIO_20_DIRECTION" VALUE="out"/>
        <PARAMETER NAME="PCW_MIO_20_SLEW" VALUE="fast"/>
        <PARAMETER NAME="PCW_MIO_21_PULLUP" VALUE="disabled"/>
        <PARAMETER NAME="PCW_MIO_21_IOTYPE" VALUE="LVCMOS 2.5V"/>
        <PARAMETER NAME="PCW_MIO_21_DIRECTION" VALUE="out"/>
        <PARAMETER NAME="PCW_MIO_21_SLEW" VALUE="fast"/>
        <PARAMETER NAME="PCW_MIO_22_PULLUP" VALUE="disabled"/>
        <PARAMETER NAME="PCW_MIO_22_IOTYPE" VALUE="LVCMOS 2.5V"/>
        <PARAMETER NAME="PCW_MIO_22_DIRECTION" VALUE="in"/>
        <PARAMETER NAME="PCW_MIO_22_SLEW" VALUE="fast"/>
        <PARAMETER NAME="PCW_MIO_23_PULLUP" VALUE="disabled"/>
        <PARAMETER NAME="PCW_MIO_23_IOTYPE" VALUE="LVCMOS 2.5V"/>
        <PARAMETER NAME="PCW_MIO_23_DIRECTION" VALUE="in"/>
        <PARAMETER NAME="PCW_MIO_23_SLEW" VALUE="fast"/>
        <PARAMETER NAME="PCW_MIO_24_PULLUP" VALUE="disabled"/>
        <PARAMETER NAME="PCW_MIO_24_IOTYPE" VALUE="LVCMOS 2.5V"/>
        <PARAMETER NAME="PCW_MIO_24_DIRECTION" VALUE="in"/>
        <PARAMETER NAME="PCW_MIO_24_SLEW" VALUE="fast"/>
        <PARAMETER NAME="PCW_MIO_25_PULLUP" VALUE="disabled"/>
        <PARAMETER NAME="PCW_MIO_25_IOTYPE" VALUE="LVCMOS 2.5V"/>
        <PARAMETER NAME="PCW_MIO_25_DIRECTION" VALUE="in"/>
        <PARAMETER NAME="PCW_MIO_25_SLEW" VALUE="fast"/>
        <PARAMETER NAME="PCW_MIO_26_PULLUP" VALUE="disabled"/>
        <PARAMETER NAME="PCW_MIO_26_IOTYPE" VALUE="LVCMOS 2.5V"/>
        <PARAMETER NAME="PCW_MIO_26_DIRECTION" VALUE="in"/>
        <PARAMETER NAME="PCW_MIO_26_SLEW" VALUE="fast"/>
        <PARAMETER NAME="PCW_MIO_27_PULLUP" VALUE="disabled"/>
        <PARAMETER NAME="PCW_MIO_27_IOTYPE" VALUE="LVCMOS 2.5V"/>
        <PARAMETER NAME="PCW_MIO_27_DIRECTION" VALUE="in"/>
        <PARAMETER NAME="PCW_MIO_27_SLEW" VALUE="fast"/>
        <PARAMETER NAME="PCW_MIO_28_PULLUP" VALUE="enabled"/>
        <PARAMETER NAME="PCW_MIO_28_IOTYPE" VALUE="LVCMOS 2.5V"/>
        <PARAMETER NAME="PCW_MIO_28_DIRECTION" VALUE="inout"/>
        <PARAMETER NAME="PCW_MIO_28_SLEW" VALUE="fast"/>
        <PARAMETER NAME="PCW_MIO_29_PULLUP" VALUE="enabled"/>
        <PARAMETER NAME="PCW_MIO_29_IOTYPE" VALUE="LVCMOS 2.5V"/>
        <PARAMETER NAME="PCW_MIO_29_DIRECTION" VALUE="in"/>
        <PARAMETER NAME="PCW_MIO_29_SLEW" VALUE="fast"/>
        <PARAMETER NAME="PCW_MIO_30_PULLUP" VALUE="enabled"/>
        <PARAMETER NAME="PCW_MIO_30_IOTYPE" VALUE="LVCMOS 2.5V"/>
        <PARAMETER NAME="PCW_MIO_30_DIRECTION" VALUE="out"/>
        <PARAMETER NAME="PCW_MIO_30_SLEW" VALUE="fast"/>
        <PARAMETER NAME="PCW_MIO_31_PULLUP" VALUE="enabled"/>
        <PARAMETER NAME="PCW_MIO_31_IOTYPE" VALUE="LVCMOS 2.5V"/>
        <PARAMETER NAME="PCW_MIO_31_DIRECTION" VALUE="in"/>
        <PARAMETER NAME="PCW_MIO_31_SLEW" VALUE="fast"/>
        <PARAMETER NAME="PCW_MIO_32_PULLUP" VALUE="enabled"/>
        <PARAMETER NAME="PCW_MIO_32_IOTYPE" VALUE="LVCMOS 2.5V"/>
        <PARAMETER NAME="PCW_MIO_32_DIRECTION" VALUE="inout"/>
        <PARAMETER NAME="PCW_MIO_32_SLEW" VALUE="fast"/>
        <PARAMETER NAME="PCW_MIO_33_PULLUP" VALUE="enabled"/>
        <PARAMETER NAME="PCW_MIO_33_IOTYPE" VALUE="LVCMOS 2.5V"/>
        <PARAMETER NAME="PCW_MIO_33_DIRECTION" VALUE="inout"/>
        <PARAMETER NAME="PCW_MIO_33_SLEW" VALUE="fast"/>
        <PARAMETER NAME="PCW_MIO_34_PULLUP" VALUE="enabled"/>
        <PARAMETER NAME="PCW_MIO_34_IOTYPE" VALUE="LVCMOS 2.5V"/>
        <PARAMETER NAME="PCW_MIO_34_DIRECTION" VALUE="inout"/>
        <PARAMETER NAME="PCW_MIO_34_SLEW" VALUE="fast"/>
        <PARAMETER NAME="PCW_MIO_35_PULLUP" VALUE="enabled"/>
        <PARAMETER NAME="PCW_MIO_35_IOTYPE" VALUE="LVCMOS 2.5V"/>
        <PARAMETER NAME="PCW_MIO_35_DIRECTION" VALUE="inout"/>
        <PARAMETER NAME="PCW_MIO_35_SLEW" VALUE="fast"/>
        <PARAMETER NAME="PCW_MIO_36_PULLUP" VALUE="enabled"/>
        <PARAMETER NAME="PCW_MIO_36_IOTYPE" VALUE="LVCMOS 2.5V"/>
        <PARAMETER NAME="PCW_MIO_36_DIRECTION" VALUE="in"/>
        <PARAMETER NAME="PCW_MIO_36_SLEW" VALUE="fast"/>
        <PARAMETER NAME="PCW_MIO_37_PULLUP" VALUE="enabled"/>
        <PARAMETER NAME="PCW_MIO_37_IOTYPE" VALUE="LVCMOS 2.5V"/>
        <PARAMETER NAME="PCW_MIO_37_DIRECTION" VALUE="inout"/>
        <PARAMETER NAME="PCW_MIO_37_SLEW" VALUE="fast"/>
        <PARAMETER NAME="PCW_MIO_38_PULLUP" VALUE="enabled"/>
        <PARAMETER NAME="PCW_MIO_38_IOTYPE" VALUE="LVCMOS 2.5V"/>
        <PARAMETER NAME="PCW_MIO_38_DIRECTION" VALUE="inout"/>
        <PARAMETER NAME="PCW_MIO_38_SLEW" VALUE="fast"/>
        <PARAMETER NAME="PCW_MIO_39_PULLUP" VALUE="enabled"/>
        <PARAMETER NAME="PCW_MIO_39_IOTYPE" VALUE="LVCMOS 2.5V"/>
        <PARAMETER NAME="PCW_MIO_39_DIRECTION" VALUE="inout"/>
        <PARAMETER NAME="PCW_MIO_39_SLEW" VALUE="fast"/>
        <PARAMETER NAME="PCW_MIO_40_PULLUP" VALUE="enabled"/>
        <PARAMETER NAME="PCW_MIO_40_IOTYPE" VALUE="LVCMOS 2.5V"/>
        <PARAMETER NAME="PCW_MIO_40_DIRECTION" VALUE="inout"/>
        <PARAMETER NAME="PCW_MIO_40_SLEW" VALUE="slow"/>
        <PARAMETER NAME="PCW_MIO_41_PULLUP" VALUE="enabled"/>
        <PARAMETER NAME="PCW_MIO_41_IOTYPE" VALUE="LVCMOS 2.5V"/>
        <PARAMETER NAME="PCW_MIO_41_DIRECTION" VALUE="inout"/>
        <PARAMETER NAME="PCW_MIO_41_SLEW" VALUE="slow"/>
        <PARAMETER NAME="PCW_MIO_42_PULLUP" VALUE="enabled"/>
        <PARAMETER NAME="PCW_MIO_42_IOTYPE" VALUE="LVCMOS 2.5V"/>
        <PARAMETER NAME="PCW_MIO_42_DIRECTION" VALUE="inout"/>
        <PARAMETER NAME="PCW_MIO_42_SLEW" VALUE="slow"/>
        <PARAMETER NAME="PCW_MIO_43_PULLUP" VALUE="enabled"/>
        <PARAMETER NAME="PCW_MIO_43_IOTYPE" VALUE="LVCMOS 2.5V"/>
        <PARAMETER NAME="PCW_MIO_43_DIRECTION" VALUE="inout"/>
        <PARAMETER NAME="PCW_MIO_43_SLEW" VALUE="slow"/>
        <PARAMETER NAME="PCW_MIO_44_PULLUP" VALUE="enabled"/>
        <PARAMETER NAME="PCW_MIO_44_IOTYPE" VALUE="LVCMOS 2.5V"/>
        <PARAMETER NAME="PCW_MIO_44_DIRECTION" VALUE="inout"/>
        <PARAMETER NAME="PCW_MIO_44_SLEW" VALUE="slow"/>
        <PARAMETER NAME="PCW_MIO_45_PULLUP" VALUE="enabled"/>
        <PARAMETER NAME="PCW_MIO_45_IOTYPE" VALUE="LVCMOS 2.5V"/>
        <PARAMETER NAME="PCW_MIO_45_DIRECTION" VALUE="inout"/>
        <PARAMETER NAME="PCW_MIO_45_SLEW" VALUE="slow"/>
        <PARAMETER NAME="PCW_MIO_46_PULLUP" VALUE="enabled"/>
        <PARAMETER NAME="PCW_MIO_46_IOTYPE" VALUE="LVCMOS 2.5V"/>
        <PARAMETER NAME="PCW_MIO_46_DIRECTION" VALUE="in"/>
        <PARAMETER NAME="PCW_MIO_46_SLEW" VALUE="slow"/>
        <PARAMETER NAME="PCW_MIO_47_PULLUP" VALUE="enabled"/>
        <PARAMETER NAME="PCW_MIO_47_IOTYPE" VALUE="LVCMOS 2.5V"/>
        <PARAMETER NAME="PCW_MIO_47_DIRECTION" VALUE="in"/>
        <PARAMETER NAME="PCW_MIO_47_SLEW" VALUE="slow"/>
        <PARAMETER NAME="PCW_MIO_48_PULLUP" VALUE="enabled"/>
        <PARAMETER NAME="PCW_MIO_48_IOTYPE" VALUE="LVCMOS 2.5V"/>
        <PARAMETER NAME="PCW_MIO_48_DIRECTION" VALUE="out"/>
        <PARAMETER NAME="PCW_MIO_48_SLEW" VALUE="slow"/>
        <PARAMETER NAME="PCW_MIO_49_PULLUP" VALUE="enabled"/>
        <PARAMETER NAME="PCW_MIO_49_IOTYPE" VALUE="LVCMOS 2.5V"/>
        <PARAMETER NAME="PCW_MIO_49_DIRECTION" VALUE="inout"/>
        <PARAMETER NAME="PCW_MIO_49_SLEW" VALUE="slow"/>
        <PARAMETER NAME="PCW_MIO_50_PULLUP" VALUE="enabled"/>
        <PARAMETER NAME="PCW_MIO_50_IOTYPE" VALUE="LVCMOS 2.5V"/>
        <PARAMETER NAME="PCW_MIO_50_DIRECTION" VALUE="inout"/>
        <PARAMETER NAME="PCW_MIO_50_SLEW" VALUE="slow"/>
        <PARAMETER NAME="PCW_MIO_51_PULLUP" VALUE="enabled"/>
        <PARAMETER NAME="PCW_MIO_51_IOTYPE" VALUE="LVCMOS 2.5V"/>
        <PARAMETER NAME="PCW_MIO_51_DIRECTION" VALUE="inout"/>
        <PARAMETER NAME="PCW_MIO_51_SLEW" VALUE="slow"/>
        <PARAMETER NAME="PCW_MIO_52_PULLUP" VALUE="enabled"/>
        <PARAMETER NAME="PCW_MIO_52_IOTYPE" VALUE="LVCMOS 2.5V"/>
        <PARAMETER NAME="PCW_MIO_52_DIRECTION" VALUE="out"/>
        <PARAMETER NAME="PCW_MIO_52_SLEW" VALUE="slow"/>
        <PARAMETER NAME="PCW_MIO_53_PULLUP" VALUE="enabled"/>
        <PARAMETER NAME="PCW_MIO_53_IOTYPE" VALUE="LVCMOS 2.5V"/>
        <PARAMETER NAME="PCW_MIO_53_DIRECTION" VALUE="inout"/>
        <PARAMETER NAME="PCW_MIO_53_SLEW" VALUE="slow"/>
        <PARAMETER NAME="preset" VALUE="None"/>
        <PARAMETER NAME="PCW_UIPARAM_GENERATE_SUMMARY" VALUE="NA"/>
        <PARAMETER NAME="PCW_MIO_TREE_PERIPHERALS" VALUE="GPIO#GPIO#GPIO#GPIO#GPIO#GPIO#GPIO#GPIO#UART 1#UART 1#SPI 1#SPI 1#SPI 1#SPI 1#UART 0#UART 0#Enet 0#Enet 0#Enet 0#Enet 0#Enet 0#Enet 0#Enet 0#Enet 0#Enet 0#Enet 0#Enet 0#Enet 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#SD 0#SD 0#SD 0#SD 0#SD 0#SD 0#SD 0#SD 0#USB Reset#GPIO#I2C 0#I2C 0#Enet 0#Enet 0"/>
        <PARAMETER NAME="PCW_MIO_TREE_SIGNALS" VALUE="gpio[0]#gpio[1]#gpio[2]#gpio[3]#gpio[4]#gpio[5]#gpio[6]#gpio[7]#tx#rx#mosi#miso#sclk#ss[0]#rx#tx#tx_clk#txd[0]#txd[1]#txd[2]#txd[3]#tx_ctl#rx_clk#rxd[0]#rxd[1]#rxd[2]#rxd[3]#rx_ctl#data[4]#dir#stp#nxt#data[0]#data[1]#data[2]#data[3]#clk#data[5]#data[6]#data[7]#clk#cmd#data[0]#data[1]#data[2]#data[3]#cd#wp#reset#gpio[49]#scl#sda#mdc#mdio"/>
        <PARAMETER NAME="PCW_PS7_SI_REV" VALUE="PRODUCTION"/>
        <PARAMETER NAME="PCW_FPGA_FCLK0_ENABLE" VALUE="1"/>
        <PARAMETER NAME="PCW_FPGA_FCLK1_ENABLE" VALUE="0"/>
        <PARAMETER NAME="PCW_FPGA_FCLK2_ENABLE" VALUE="0"/>
        <PARAMETER NAME="PCW_FPGA_FCLK3_ENABLE" VALUE="0"/>
        <PARAMETER NAME="PCW_NOR_SRAM_CS0_T_TR" VALUE="1"/>
        <PARAMETER NAME="PCW_NOR_SRAM_CS0_T_PC" VALUE="1"/>
        <PARAMETER NAME="PCW_NOR_SRAM_CS0_T_WP" VALUE="1"/>
        <PARAMETER NAME="PCW_NOR_SRAM_CS0_T_CEOE" VALUE="1"/>
        <PARAMETER NAME="PCW_NOR_SRAM_CS0_T_WC" VALUE="11"/>
        <PARAMETER NAME="PCW_NOR_SRAM_CS0_T_RC" VALUE="11"/>
        <PARAMETER NAME="PCW_NOR_SRAM_CS0_WE_TIME" VALUE="0"/>
        <PARAMETER NAME="PCW_NOR_SRAM_CS1_T_TR" VALUE="1"/>
        <PARAMETER NAME="PCW_NOR_SRAM_CS1_T_PC" VALUE="1"/>
        <PARAMETER NAME="PCW_NOR_SRAM_CS1_T_WP" VALUE="1"/>
        <PARAMETER NAME="PCW_NOR_SRAM_CS1_T_CEOE" VALUE="1"/>
        <PARAMETER NAME="PCW_NOR_SRAM_CS1_T_WC" VALUE="11"/>
        <PARAMETER NAME="PCW_NOR_SRAM_CS1_T_RC" VALUE="11"/>
        <PARAMETER NAME="PCW_NOR_SRAM_CS1_WE_TIME" VALUE="0"/>
        <PARAMETER NAME="PCW_NOR_CS0_T_TR" VALUE="1"/>
        <PARAMETER NAME="PCW_NOR_CS0_T_PC" VALUE="1"/>
        <PARAMETER NAME="PCW_NOR_CS0_T_WP" VALUE="1"/>
        <PARAMETER NAME="PCW_NOR_CS0_T_CEOE" VALUE="1"/>
        <PARAMETER NAME="PCW_NOR_CS0_T_WC" VALUE="11"/>
        <PARAMETER NAME="PCW_NOR_CS0_T_RC" VALUE="11"/>
        <PARAMETER NAME="PCW_NOR_CS0_WE_TIME" VALUE="0"/>
        <PARAMETER NAME="PCW_NOR_CS1_T_TR" VALUE="1"/>
        <PARAMETER NAME="PCW_NOR_CS1_T_PC" VALUE="1"/>
        <PARAMETER NAME="PCW_NOR_CS1_T_WP" VALUE="1"/>
        <PARAMETER NAME="PCW_NOR_CS1_T_CEOE" VALUE="1"/>
        <PARAMETER NAME="PCW_NOR_CS1_T_WC" VALUE="11"/>
        <PARAMETER NAME="PCW_NOR_CS1_T_RC" VALUE="11"/>
        <PARAMETER NAME="PCW_NOR_CS1_WE_TIME" VALUE="0"/>
        <PARAMETER NAME="PCW_NAND_CYCLES_T_RR" VALUE="1"/>
        <PARAMETER NAME="PCW_NAND_CYCLES_T_AR" VALUE="1"/>
        <PARAMETER NAME="PCW_NAND_CYCLES_T_CLR" VALUE="1"/>
        <PARAMETER NAME="PCW_NAND_CYCLES_T_WP" VALUE="1"/>
        <PARAMETER NAME="PCW_NAND_CYCLES_T_REA" VALUE="1"/>
        <PARAMETER NAME="PCW_NAND_CYCLES_T_WC" VALUE="11"/>
        <PARAMETER NAME="PCW_NAND_CYCLES_T_RC" VALUE="11"/>
        <PARAMETER NAME="PCW_SMC_CYCLE_T0" VALUE="NA"/>
        <PARAMETER NAME="PCW_SMC_CYCLE_T1" VALUE="NA"/>
        <PARAMETER NAME="PCW_SMC_CYCLE_T2" VALUE="NA"/>
        <PARAMETER NAME="PCW_SMC_CYCLE_T3" VALUE="NA"/>
        <PARAMETER NAME="PCW_SMC_CYCLE_T4" VALUE="NA"/>
        <PARAMETER NAME="PCW_SMC_CYCLE_T5" VALUE="NA"/>
        <PARAMETER NAME="PCW_SMC_CYCLE_T6" VALUE="NA"/>
        <PARAMETER NAME="PCW_PACKAGE_NAME" VALUE="clg400"/>
        <PARAMETER NAME="PCW_PLL_BYPASSMODE_ENABLE" VALUE="0"/>
        <PARAMETER NAME="Component_Name" VALUE="system_ps_0_0"/>
        <PARAMETER NAME="EDK_IPTYPE" VALUE="PERIPHERAL"/>
      </PARAMETERS>
      <PORTS>
        <PORT DIR="I" LEFT="63" NAME="GPIO_I" RIGHT="0" SIGIS="undef"/>
        <PORT DIR="O" LEFT="63" NAME="GPIO_O" RIGHT="0" SIGIS="undef"/>
        <PORT DIR="O" LEFT="63" NAME="GPIO_T" RIGHT="0" SIGIS="undef"/>
        <PORT DIR="I" NAME="SPI0_SCLK_I" SIGIS="undef"/>
        <PORT DIR="O" NAME="SPI0_SCLK_O" SIGIS="undef"/>
        <PORT DIR="O" NAME="SPI0_SCLK_T" SIGIS="undef"/>
        <PORT DIR="I" NAME="SPI0_MOSI_I" SIGIS="undef"/>
        <PORT DIR="O" NAME="SPI0_MOSI_O" SIGIS="undef"/>
        <PORT DIR="O" NAME="SPI0_MOSI_T" SIGIS="undef"/>
        <PORT DIR="I" NAME="SPI0_MISO_I" SIGIS="undef"/>
        <PORT DIR="O" NAME="SPI0_MISO_O" SIGIS="undef"/>
        <PORT DIR="O" NAME="SPI0_MISO_T" SIGIS="undef"/>
        <PORT DIR="I" NAME="SPI0_SS_I" SIGIS="undef"/>
        <PORT DIR="O" NAME="SPI0_SS_O" SIGIS="undef"/>
        <PORT DIR="O" NAME="SPI0_SS1_O" SIGIS="undef"/>
        <PORT DIR="O" NAME="SPI0_SS2_O" SIGIS="undef"/>
        <PORT DIR="O" NAME="SPI0_SS_T" SIGIS="undef"/>
        <PORT DIR="O" LEFT="1" NAME="USB0_PORT_INDCTL" RIGHT="0" SIGIS="undef"/>
        <PORT DIR="O" NAME="USB0_VBUS_PWRSELECT" SIGIS="undef"/>
        <PORT DIR="I" NAME="USB0_VBUS_PWRFAULT" SIGIS="undef"/>
        <PORT DIR="O" NAME="M_AXI_GP0_ARVALID" SIGIS="undef" SIGNAME="hub_0_s_axi_arvalid">
          <CONNECTIONS>
            <CONNECTION INSTANCE="hub_0" PORT="s_axi_arvalid"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" NAME="M_AXI_GP0_AWVALID" SIGIS="undef" SIGNAME="hub_0_s_axi_awvalid">
          <CONNECTIONS>
            <CONNECTION INSTANCE="hub_0" PORT="s_axi_awvalid"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" NAME="M_AXI_GP0_BREADY" SIGIS="undef" SIGNAME="hub_0_s_axi_bready">
          <CONNECTIONS>
            <CONNECTION INSTANCE="hub_0" PORT="s_axi_bready"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" NAME="M_AXI_GP0_RREADY" SIGIS="undef" SIGNAME="hub_0_s_axi_rready">
          <CONNECTIONS>
            <CONNECTION INSTANCE="hub_0" PORT="s_axi_rready"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" NAME="M_AXI_GP0_WLAST" SIGIS="undef" SIGNAME="hub_0_s_axi_wlast">
          <CONNECTIONS>
            <CONNECTION INSTANCE="hub_0" PORT="s_axi_wlast"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" NAME="M_AXI_GP0_WVALID" SIGIS="undef" SIGNAME="hub_0_s_axi_wvalid">
          <CONNECTIONS>
            <CONNECTION INSTANCE="hub_0" PORT="s_axi_wvalid"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" LEFT="11" NAME="M_AXI_GP0_ARID" RIGHT="0" SIGIS="undef" SIGNAME="hub_0_s_axi_arid">
          <CONNECTIONS>
            <CONNECTION INSTANCE="hub_0" PORT="s_axi_arid"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" LEFT="11" NAME="M_AXI_GP0_AWID" RIGHT="0" SIGIS="undef" SIGNAME="hub_0_s_axi_awid">
          <CONNECTIONS>
            <CONNECTION INSTANCE="hub_0" PORT="s_axi_awid"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" LEFT="11" NAME="M_AXI_GP0_WID" RIGHT="0" SIGIS="undef"/>
        <PORT DIR="O" LEFT="1" NAME="M_AXI_GP0_ARBURST" RIGHT="0" SIGIS="undef"/>
        <PORT DIR="O" LEFT="1" NAME="M_AXI_GP0_ARLOCK" RIGHT="0" SIGIS="undef"/>
        <PORT DIR="O" LEFT="2" NAME="M_AXI_GP0_ARSIZE" RIGHT="0" SIGIS="undef"/>
        <PORT DIR="O" LEFT="1" NAME="M_AXI_GP0_AWBURST" RIGHT="0" SIGIS="undef"/>
        <PORT DIR="O" LEFT="1" NAME="M_AXI_GP0_AWLOCK" RIGHT="0" SIGIS="undef"/>
        <PORT DIR="O" LEFT="2" NAME="M_AXI_GP0_AWSIZE" RIGHT="0" SIGIS="undef"/>
        <PORT DIR="O" LEFT="2" NAME="M_AXI_GP0_ARPROT" RIGHT="0" SIGIS="undef"/>
        <PORT DIR="O" LEFT="2" NAME="M_AXI_GP0_AWPROT" RIGHT="0" SIGIS="undef"/>
        <PORT DIR="O" LEFT="31" NAME="M_AXI_GP0_ARADDR" RIGHT="0" SIGIS="undef" SIGNAME="hub_0_s_axi_araddr">
          <CONNECTIONS>
            <CONNECTION INSTANCE="hub_0" PORT="s_axi_araddr"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" LEFT="31" NAME="M_AXI_GP0_AWADDR" RIGHT="0" SIGIS="undef" SIGNAME="hub_0_s_axi_awaddr">
          <CONNECTIONS>
            <CONNECTION INSTANCE="hub_0" PORT="s_axi_awaddr"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" LEFT="31" NAME="M_AXI_GP0_WDATA" RIGHT="0" SIGIS="undef" SIGNAME="hub_0_s_axi_wdata">
          <CONNECTIONS>
            <CONNECTION INSTANCE="hub_0" PORT="s_axi_wdata"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" LEFT="3" NAME="M_AXI_GP0_ARCACHE" RIGHT="0" SIGIS="undef"/>
        <PORT DIR="O" LEFT="3" NAME="M_AXI_GP0_ARLEN" RIGHT="0" SIGIS="undef" SIGNAME="hub_0_s_axi_arlen">
          <CONNECTIONS>
            <CONNECTION INSTANCE="hub_0" PORT="s_axi_arlen"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" LEFT="3" NAME="M_AXI_GP0_ARQOS" RIGHT="0" SIGIS="undef"/>
        <PORT DIR="O" LEFT="3" NAME="M_AXI_GP0_AWCACHE" RIGHT="0" SIGIS="undef"/>
        <PORT DIR="O" LEFT="3" NAME="M_AXI_GP0_AWLEN" RIGHT="0" SIGIS="undef"/>
        <PORT DIR="O" LEFT="3" NAME="M_AXI_GP0_AWQOS" RIGHT="0" SIGIS="undef"/>
        <PORT DIR="O" LEFT="3" NAME="M_AXI_GP0_WSTRB" RIGHT="0" SIGIS="undef" SIGNAME="hub_0_s_axi_wstrb">
          <CONNECTIONS>
            <CONNECTION INSTANCE="hub_0" PORT="s_axi_wstrb"/>
          </CONNECTIONS>
        </PORT>
        <PORT CLKFREQUENCY="122880000" DIR="I" NAME="M_AXI_GP0_ACLK" SIGIS="clk" SIGNAME="pll_0_clk_out1">
          <CONNECTIONS>
            <CONNECTION INSTANCE="pll_0" PORT="clk_out1"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" NAME="M_AXI_GP0_ARREADY" SIGIS="undef" SIGNAME="hub_0_s_axi_arready">
          <CONNECTIONS>
            <CONNECTION INSTANCE="hub_0" PORT="s_axi_arready"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" NAME="M_AXI_GP0_AWREADY" SIGIS="undef" SIGNAME="hub_0_s_axi_awready">
          <CONNECTIONS>
            <CONNECTION INSTANCE="hub_0" PORT="s_axi_awready"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" NAME="M_AXI_GP0_BVALID" SIGIS="undef" SIGNAME="hub_0_s_axi_bvalid">
          <CONNECTIONS>
            <CONNECTION INSTANCE="hub_0" PORT="s_axi_bvalid"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" NAME="M_AXI_GP0_RLAST" SIGIS="undef" SIGNAME="hub_0_s_axi_rlast">
          <CONNECTIONS>
            <CONNECTION INSTANCE="hub_0" PORT="s_axi_rlast"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" NAME="M_AXI_GP0_RVALID" SIGIS="undef" SIGNAME="hub_0_s_axi_rvalid">
          <CONNECTIONS>
            <CONNECTION INSTANCE="hub_0" PORT="s_axi_rvalid"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" NAME="M_AXI_GP0_WREADY" SIGIS="undef" SIGNAME="hub_0_s_axi_wready">
          <CONNECTIONS>
            <CONNECTION INSTANCE="hub_0" PORT="s_axi_wready"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" LEFT="11" NAME="M_AXI_GP0_BID" RIGHT="0" SIGIS="undef" SIGNAME="hub_0_s_axi_bid">
          <CONNECTIONS>
            <CONNECTION INSTANCE="hub_0" PORT="s_axi_bid"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" LEFT="11" NAME="M_AXI_GP0_RID" RIGHT="0" SIGIS="undef" SIGNAME="hub_0_s_axi_rid">
          <CONNECTIONS>
            <CONNECTION INSTANCE="hub_0" PORT="s_axi_rid"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" LEFT="1" NAME="M_AXI_GP0_BRESP" RIGHT="0" SIGIS="undef"/>
        <PORT DIR="I" LEFT="1" NAME="M_AXI_GP0_RRESP" RIGHT="0" SIGIS="undef"/>
        <PORT DIR="I" LEFT="31" NAME="M_AXI_GP0_RDATA" RIGHT="0" SIGIS="undef" SIGNAME="hub_0_s_axi_rdata">
          <CONNECTIONS>
            <CONNECTION INSTANCE="hub_0" PORT="s_axi_rdata"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" NAME="S_AXI_ACP_ARREADY" SIGIS="undef"/>
        <PORT DIR="O" NAME="S_AXI_ACP_AWREADY" SIGIS="undef" SIGNAME="ps_0_S_AXI_ACP_AWREADY">
          <CONNECTIONS>
            <CONNECTION INSTANCE="writer_0" PORT="m_axi_awready"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" NAME="S_AXI_ACP_BVALID" SIGIS="undef" SIGNAME="ps_0_S_AXI_ACP_BVALID">
          <CONNECTIONS>
            <CONNECTION INSTANCE="writer_0" PORT="m_axi_bvalid"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" NAME="S_AXI_ACP_RLAST" SIGIS="undef"/>
        <PORT DIR="O" NAME="S_AXI_ACP_RVALID" SIGIS="undef"/>
        <PORT DIR="O" NAME="S_AXI_ACP_WREADY" SIGIS="undef" SIGNAME="ps_0_S_AXI_ACP_WREADY">
          <CONNECTIONS>
            <CONNECTION INSTANCE="writer_0" PORT="m_axi_wready"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" LEFT="1" NAME="S_AXI_ACP_BRESP" RIGHT="0" SIGIS="undef"/>
        <PORT DIR="O" LEFT="1" NAME="S_AXI_ACP_RRESP" RIGHT="0" SIGIS="undef"/>
        <PORT DIR="O" LEFT="2" NAME="S_AXI_ACP_BID" RIGHT="0" SIGIS="undef"/>
        <PORT DIR="O" LEFT="2" NAME="S_AXI_ACP_RID" RIGHT="0" SIGIS="undef"/>
        <PORT DIR="O" LEFT="63" NAME="S_AXI_ACP_RDATA" RIGHT="0" SIGIS="undef"/>
        <PORT CLKFREQUENCY="122880000" DIR="I" NAME="S_AXI_ACP_ACLK" SIGIS="clk" SIGNAME="pll_0_clk_out1">
          <CONNECTIONS>
            <CONNECTION INSTANCE="pll_0" PORT="clk_out1"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" NAME="S_AXI_ACP_ARVALID" SIGIS="undef"/>
        <PORT DIR="I" NAME="S_AXI_ACP_AWVALID" SIGIS="undef" SIGNAME="ps_0_S_AXI_ACP_AWVALID">
          <CONNECTIONS>
            <CONNECTION INSTANCE="writer_0" PORT="m_axi_awvalid"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" NAME="S_AXI_ACP_BREADY" SIGIS="undef" SIGNAME="ps_0_S_AXI_ACP_BREADY">
          <CONNECTIONS>
            <CONNECTION INSTANCE="writer_0" PORT="m_axi_bready"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" NAME="S_AXI_ACP_RREADY" SIGIS="undef"/>
        <PORT DIR="I" NAME="S_AXI_ACP_WLAST" SIGIS="undef" SIGNAME="ps_0_S_AXI_ACP_WLAST">
          <CONNECTIONS>
            <CONNECTION INSTANCE="writer_0" PORT="m_axi_wlast"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" NAME="S_AXI_ACP_WVALID" SIGIS="undef" SIGNAME="ps_0_S_AXI_ACP_WVALID">
          <CONNECTIONS>
            <CONNECTION INSTANCE="writer_0" PORT="m_axi_wvalid"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" LEFT="2" NAME="S_AXI_ACP_ARID" RIGHT="0" SIGIS="undef"/>
        <PORT DIR="I" LEFT="2" NAME="S_AXI_ACP_ARPROT" RIGHT="0" SIGIS="undef"/>
        <PORT DIR="I" LEFT="2" NAME="S_AXI_ACP_AWID" RIGHT="0" SIGIS="undef" SIGNAME="ps_0_S_AXI_ACP_AWID">
          <CONNECTIONS>
            <CONNECTION INSTANCE="writer_0" PORT="m_axi_awid"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" LEFT="2" NAME="S_AXI_ACP_AWPROT" RIGHT="0" SIGIS="undef"/>
        <PORT DIR="I" LEFT="2" NAME="S_AXI_ACP_WID" RIGHT="0" SIGIS="undef" SIGNAME="ps_0_S_AXI_ACP_WID">
          <CONNECTIONS>
            <CONNECTION INSTANCE="writer_0" PORT="m_axi_wid"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" LEFT="31" NAME="S_AXI_ACP_ARADDR" RIGHT="0" SIGIS="undef"/>
        <PORT DIR="I" LEFT="31" NAME="S_AXI_ACP_AWADDR" RIGHT="0" SIGIS="undef" SIGNAME="ps_0_S_AXI_ACP_AWADDR">
          <CONNECTIONS>
            <CONNECTION INSTANCE="writer_0" PORT="m_axi_awaddr"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" LEFT="3" NAME="S_AXI_ACP_ARCACHE" RIGHT="0" SIGIS="undef"/>
        <PORT DIR="I" LEFT="3" NAME="S_AXI_ACP_ARLEN" RIGHT="0" SIGIS="undef"/>
        <PORT DIR="I" LEFT="3" NAME="S_AXI_ACP_ARQOS" RIGHT="0" SIGIS="undef"/>
        <PORT DIR="I" LEFT="3" NAME="S_AXI_ACP_AWCACHE" RIGHT="0" SIGIS="undef" SIGNAME="ps_0_S_AXI_ACP_AWCACHE">
          <CONNECTIONS>
            <CONNECTION INSTANCE="writer_0" PORT="m_axi_awcache"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" LEFT="3" NAME="S_AXI_ACP_AWLEN" RIGHT="0" SIGIS="undef" SIGNAME="ps_0_S_AXI_ACP_AWLEN">
          <CONNECTIONS>
            <CONNECTION INSTANCE="writer_0" PORT="m_axi_awlen"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" LEFT="3" NAME="S_AXI_ACP_AWQOS" RIGHT="0" SIGIS="undef"/>
        <PORT DIR="I" LEFT="1" NAME="S_AXI_ACP_ARBURST" RIGHT="0" SIGIS="undef"/>
        <PORT DIR="I" LEFT="1" NAME="S_AXI_ACP_ARLOCK" RIGHT="0" SIGIS="undef"/>
        <PORT DIR="I" LEFT="2" NAME="S_AXI_ACP_ARSIZE" RIGHT="0" SIGIS="undef"/>
        <PORT DIR="I" LEFT="1" NAME="S_AXI_ACP_AWBURST" RIGHT="0" SIGIS="undef" SIGNAME="ps_0_S_AXI_ACP_AWBURST">
          <CONNECTIONS>
            <CONNECTION INSTANCE="writer_0" PORT="m_axi_awburst"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" LEFT="1" NAME="S_AXI_ACP_AWLOCK" RIGHT="0" SIGIS="undef"/>
        <PORT DIR="I" LEFT="2" NAME="S_AXI_ACP_AWSIZE" RIGHT="0" SIGIS="undef" SIGNAME="ps_0_S_AXI_ACP_AWSIZE">
          <CONNECTIONS>
            <CONNECTION INSTANCE="writer_0" PORT="m_axi_awsize"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" LEFT="4" NAME="S_AXI_ACP_ARUSER" RIGHT="0" SIGIS="undef"/>
        <PORT DIR="I" LEFT="4" NAME="S_AXI_ACP_AWUSER" RIGHT="0" SIGIS="undef"/>
        <PORT DIR="I" LEFT="63" NAME="S_AXI_ACP_WDATA" RIGHT="0" SIGIS="undef" SIGNAME="ps_0_S_AXI_ACP_WDATA">
          <CONNECTIONS>
            <CONNECTION INSTANCE="writer_0" PORT="m_axi_wdata"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" LEFT="7" NAME="S_AXI_ACP_WSTRB" RIGHT="0" SIGIS="undef" SIGNAME="ps_0_S_AXI_ACP_WSTRB">
          <CONNECTIONS>
            <CONNECTION INSTANCE="writer_0" PORT="m_axi_wstrb"/>
          </CONNECTIONS>
        </PORT>
        <PORT CLKFREQUENCY="50000000" DIR="O" NAME="FCLK_CLK0" SIGIS="clk"/>
        <PORT DIR="O" NAME="FCLK_RESET0_N" POLARITY="ACTIVE_LOW" SIGIS="rst"/>
        <PORT DIR="IO" LEFT="53" NAME="MIO" RIGHT="0" SIGIS="undef" SIGNAME="ps_0_MIO">
          <CONNECTIONS>
            <CONNECTION INSTANCE="system_imp" PORT="FIXED_IO_mio"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="IO" NAME="DDR_CAS_n" SIGIS="undef" SIGNAME="ps_0_DDR_CAS_n">
          <CONNECTIONS>
            <CONNECTION INSTANCE="system_imp" PORT="DDR_cas_n"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="IO" NAME="DDR_CKE" SIGIS="undef" SIGNAME="ps_0_DDR_CKE">
          <CONNECTIONS>
            <CONNECTION INSTANCE="system_imp" PORT="DDR_cke"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="IO" NAME="DDR_Clk_n" SIGIS="clk" SIGNAME="ps_0_DDR_Clk_n">
          <CONNECTIONS>
            <CONNECTION INSTANCE="system_imp" PORT="DDR_ck_n"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="IO" NAME="DDR_Clk" SIGIS="clk" SIGNAME="ps_0_DDR_Clk">
          <CONNECTIONS>
            <CONNECTION INSTANCE="system_imp" PORT="DDR_ck_p"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="IO" NAME="DDR_CS_n" SIGIS="undef" SIGNAME="ps_0_DDR_CS_n">
          <CONNECTIONS>
            <CONNECTION INSTANCE="system_imp" PORT="DDR_cs_n"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="IO" NAME="DDR_DRSTB" SIGIS="rst" SIGNAME="ps_0_DDR_DRSTB">
          <CONNECTIONS>
            <CONNECTION INSTANCE="system_imp" PORT="DDR_reset_n"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="IO" NAME="DDR_ODT" SIGIS="undef" SIGNAME="ps_0_DDR_ODT">
          <CONNECTIONS>
            <CONNECTION INSTANCE="system_imp" PORT="DDR_odt"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="IO" NAME="DDR_RAS_n" SIGIS="undef" SIGNAME="ps_0_DDR_RAS_n">
          <CONNECTIONS>
            <CONNECTION INSTANCE="system_imp" PORT="DDR_ras_n"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="IO" NAME="DDR_WEB" SIGIS="undef" SIGNAME="ps_0_DDR_WEB">
          <CONNECTIONS>
            <CONNECTION INSTANCE="system_imp" PORT="DDR_we_n"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="IO" LEFT="2" NAME="DDR_BankAddr" RIGHT="0" SIGIS="undef" SIGNAME="ps_0_DDR_BankAddr">
          <CONNECTIONS>
            <CONNECTION INSTANCE="system_imp" PORT="DDR_ba"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="IO" LEFT="14" NAME="DDR_Addr" RIGHT="0" SIGIS="undef" SIGNAME="ps_0_DDR_Addr">
          <CONNECTIONS>
            <CONNECTION INSTANCE="system_imp" PORT="DDR_addr"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="IO" NAME="DDR_VRN" SIGIS="undef" SIGNAME="ps_0_DDR_VRN">
          <CONNECTIONS>
            <CONNECTION INSTANCE="system_imp" PORT="FIXED_IO_ddr_vrn"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="IO" NAME="DDR_VRP" SIGIS="undef" SIGNAME="ps_0_DDR_VRP">
          <CONNECTIONS>
            <CONNECTION INSTANCE="system_imp" PORT="FIXED_IO_ddr_vrp"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="IO" LEFT="3" NAME="DDR_DM" RIGHT="0" SIGIS="undef" SIGNAME="ps_0_DDR_DM">
          <CONNECTIONS>
            <CONNECTION INSTANCE="system_imp" PORT="DDR_dm"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="IO" LEFT="31" NAME="DDR_DQ" RIGHT="0" SIGIS="undef" SIGNAME="ps_0_DDR_DQ">
          <CONNECTIONS>
            <CONNECTION INSTANCE="system_imp" PORT="DDR_dq"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="IO" LEFT="3" NAME="DDR_DQS_n" RIGHT="0" SIGIS="undef" SIGNAME="ps_0_DDR_DQS_n">
          <CONNECTIONS>
            <CONNECTION INSTANCE="system_imp" PORT="DDR_dqs_n"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="IO" LEFT="3" NAME="DDR_DQS" RIGHT="0" SIGIS="undef" SIGNAME="ps_0_DDR_DQS">
          <CONNECTIONS>
            <CONNECTION INSTANCE="system_imp" PORT="DDR_dqs_p"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="IO" NAME="PS_SRSTB" SIGIS="undef" SIGNAME="ps_0_PS_SRSTB">
          <CONNECTIONS>
            <CONNECTION INSTANCE="system_imp" PORT="FIXED_IO_ps_srstb"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="IO" NAME="PS_CLK" SIGIS="undef" SIGNAME="ps_0_PS_CLK">
          <CONNECTIONS>
            <CONNECTION INSTANCE="system_imp" PORT="FIXED_IO_ps_clk"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="IO" NAME="PS_PORB" SIGIS="undef" SIGNAME="ps_0_PS_PORB">
          <CONNECTIONS>
            <CONNECTION INSTANCE="system_imp" PORT="FIXED_IO_ps_porb"/>
          </CONNECTIONS>
        </PORT>
      </PORTS>
      <BUSINTERFACES>
        <BUSINTERFACE BUSNAME="__NOC__" NAME="GPIO_0" TYPE="INITIATOR" VLNV="xilinx.com:interface:gpio:1.0">
          <PORTMAPS>
            <PORTMAP LOGICAL="TRI_I" PHYSICAL="GPIO_I"/>
            <PORTMAP LOGICAL="TRI_O" PHYSICAL="GPIO_O"/>
            <PORTMAP LOGICAL="TRI_T" PHYSICAL="GPIO_T"/>
          </PORTMAPS>
        </BUSINTERFACE>
        <BUSINTERFACE BUSNAME="ps_0_DDR" DATAWIDTH="8" NAME="DDR" TYPE="INITIATOR" VLNV="xilinx.com:interface:ddrx:1.0">
          <PARAMETER NAME="CAN_DEBUG" VALUE="false"/>
          <PARAMETER NAME="TIMEPERIOD_PS" VALUE="1250"/>
          <PARAMETER NAME="MEMORY_TYPE" VALUE="COMPONENTS"/>
          <PARAMETER NAME="MEMORY_PART"/>
          <PARAMETER NAME="DATA_WIDTH" VALUE="8"/>
          <PARAMETER NAME="CS_ENABLED" VALUE="true"/>
          <PARAMETER NAME="DATA_MASK_ENABLED" VALUE="true"/>
          <PARAMETER NAME="SLOT" VALUE="Single"/>
          <PARAMETER NAME="CUSTOM_PARTS"/>
          <PARAMETER NAME="MEM_ADDR_MAP" VALUE="ROW_COLUMN_BANK"/>
          <PARAMETER NAME="BURST_LENGTH" VALUE="8"/>
          <PARAMETER NAME="AXI_ARBITRATION_SCHEME" VALUE="TDM"/>
          <PARAMETER NAME="CAS_LATENCY" VALUE="11"/>
          <PARAMETER NAME="CAS_WRITE_LATENCY" VALUE="11"/>
          <PORTMAPS>
            <PORTMAP LOGICAL="CAS_N" PHYSICAL="DDR_CAS_n"/>
            <PORTMAP LOGICAL="CKE" PHYSICAL="DDR_CKE"/>
            <PORTMAP LOGICAL="CK_N" PHYSICAL="DDR_Clk_n"/>
            <PORTMAP LOGICAL="CK_P" PHYSICAL="DDR_Clk"/>
            <PORTMAP LOGICAL="CS_N" PHYSICAL="DDR_CS_n"/>
            <PORTMAP LOGICAL="RESET_N" PHYSICAL="DDR_DRSTB"/>
            <PORTMAP LOGICAL="ODT" PHYSICAL="DDR_ODT"/>
            <PORTMAP LOGICAL="RAS_N" PHYSICAL="DDR_RAS_n"/>
            <PORTMAP LOGICAL="WE_N" PHYSICAL="DDR_WEB"/>
            <PORTMAP LOGICAL="BA" PHYSICAL="DDR_BankAddr"/>
            <PORTMAP LOGICAL="ADDR" PHYSICAL="DDR_Addr"/>
            <PORTMAP LOGICAL="DM" PHYSICAL="DDR_DM"/>
            <PORTMAP LOGICAL="DQ" PHYSICAL="DDR_DQ"/>
            <PORTMAP LOGICAL="DQS_N" PHYSICAL="DDR_DQS_n"/>
            <PORTMAP LOGICAL="DQS_P" PHYSICAL="DDR_DQS"/>
          </PORTMAPS>
        </BUSINTERFACE>
        <BUSINTERFACE BUSNAME="ps_0_FIXED_IO" NAME="FIXED_IO" TYPE="INITIATOR" VLNV="xilinx.com:display_processing_system7:fixedio:1.0">
          <PARAMETER NAME="CAN_DEBUG" VALUE="false"/>
          <PORTMAPS>
            <PORTMAP LOGICAL="MIO" PHYSICAL="MIO"/>
            <PORTMAP LOGICAL="DDR_VRN" PHYSICAL="DDR_VRN"/>
            <PORTMAP LOGICAL="DDR_VRP" PHYSICAL="DDR_VRP"/>
            <PORTMAP LOGICAL="PS_SRSTB" PHYSICAL="PS_SRSTB"/>
            <PORTMAP LOGICAL="PS_CLK" PHYSICAL="PS_CLK"/>
            <PORTMAP LOGICAL="PS_PORB" PHYSICAL="PS_PORB"/>
          </PORTMAPS>
        </BUSINTERFACE>
        <BUSINTERFACE BUSNAME="__NOC__" NAME="SPI_0" TYPE="INITIATOR" VLNV="xilinx.com:interface:spi:1.0">
          <PORTMAPS>
            <PORTMAP LOGICAL="SCK_I" PHYSICAL="SPI0_SCLK_I"/>
            <PORTMAP LOGICAL="SCK_O" PHYSICAL="SPI0_SCLK_O"/>
            <PORTMAP LOGICAL="SCK_T" PHYSICAL="SPI0_SCLK_T"/>
            <PORTMAP LOGICAL="IO0_I" PHYSICAL="SPI0_MOSI_I"/>
            <PORTMAP LOGICAL="IO0_O" PHYSICAL="SPI0_MOSI_O"/>
            <PORTMAP LOGICAL="IO0_T" PHYSICAL="SPI0_MOSI_T"/>
            <PORTMAP LOGICAL="IO1_I" PHYSICAL="SPI0_MISO_I"/>
            <PORTMAP LOGICAL="IO1_O" PHYSICAL="SPI0_MISO_O"/>
            <PORTMAP LOGICAL="IO1_T" PHYSICAL="SPI0_MISO_T"/>
            <PORTMAP LOGICAL="SS_I" PHYSICAL="SPI0_SS_I"/>
            <PORTMAP LOGICAL="SS_O" PHYSICAL="SPI0_SS_O"/>
            <PORTMAP LOGICAL="SS1_O" PHYSICAL="SPI0_SS1_O"/>
            <PORTMAP LOGICAL="SS2_O" PHYSICAL="SPI0_SS2_O"/>
            <PORTMAP LOGICAL="SS_T" PHYSICAL="SPI0_SS_T"/>
          </PORTMAPS>
        </BUSINTERFACE>
        <BUSINTERFACE BUSNAME="__NOC__" NAME="USBIND_0" TYPE="INITIATOR" VLNV="xilinx.com:display_processing_system7:usbctrl:1.0">
          <PORTMAPS>
            <PORTMAP LOGICAL="PORT_INDCTL" PHYSICAL="USB0_PORT_INDCTL"/>
            <PORTMAP LOGICAL="VBUS_PWRSELECT" PHYSICAL="USB0_VBUS_PWRSELECT"/>
            <PORTMAP LOGICAL="VBUS_PWRFAULT" PHYSICAL="USB0_VBUS_PWRFAULT"/>
          </PORTMAPS>
        </BUSINTERFACE>
        <BUSINTERFACE BUSNAME="ps_0_M_AXI_GP0" DATAWIDTH="32" NAME="M_AXI_GP0" TYPE="MASTER" VLNV="xilinx.com:interface:aximm:1.0">
          <PARAMETER NAME="SUPPORTS_NARROW_BURST" VALUE="0"/>
          <PARAMETER NAME="NUM_WRITE_OUTSTANDING" VALUE="8"/>
          <PARAMETER NAME="NUM_READ_OUTSTANDING" VALUE="8"/>
          <PARAMETER NAME="DATA_WIDTH" VALUE="32"/>
          <PARAMETER NAME="PROTOCOL" VALUE="AXI3"/>
          <PARAMETER NAME="FREQ_HZ" VALUE="122880000"/>
          <PARAMETER NAME="ID_WIDTH" VALUE="12"/>
          <PARAMETER NAME="ADDR_WIDTH" VALUE="32"/>
          <PARAMETER NAME="AWUSER_WIDTH" VALUE="0"/>
          <PARAMETER NAME="ARUSER_WIDTH" VALUE="0"/>
          <PARAMETER NAME="WUSER_WIDTH" VALUE="0"/>
          <PARAMETER NAME="RUSER_WIDTH" VALUE="0"/>
          <PARAMETER NAME="BUSER_WIDTH" VALUE="0"/>
          <PARAMETER NAME="READ_WRITE_MODE" VALUE="READ_WRITE"/>
          <PARAMETER NAME="HAS_BURST" VALUE="1"/>
          <PARAMETER NAME="HAS_LOCK" VALUE="1"/>
          <PARAMETER NAME="HAS_PROT" VALUE="1"/>
          <PARAMETER NAME="HAS_CACHE" VALUE="1"/>
          <PARAMETER NAME="HAS_QOS" VALUE="1"/>
          <PARAMETER NAME="HAS_REGION" VALUE="0"/>
          <PARAMETER NAME="HAS_WSTRB" VALUE="1"/>
          <PARAMETER NAME="HAS_BRESP" VALUE="1"/>
          <PARAMETER NAME="HAS_RRESP" VALUE="1"/>
          <PARAMETER NAME="MAX_BURST_LENGTH" VALUE="16"/>
          <PARAMETER NAME="PHASE" VALUE="0.0"/>
          <PARAMETER NAME="CLK_DOMAIN" VALUE="system_pll_0_0_clk_out1"/>
          <PARAMETER NAME="NUM_READ_THREADS" VALUE="4"/>
          <PARAMETER NAME="NUM_WRITE_THREADS" VALUE="4"/>
          <PARAMETER NAME="RUSER_BITS_PER_BYTE" VALUE="0"/>
          <PARAMETER NAME="WUSER_BITS_PER_BYTE" VALUE="0"/>
          <PARAMETER NAME="INSERT_VIP" VALUE="0"/>
          <PORTMAPS>
            <PORTMAP LOGICAL="ARVALID" PHYSICAL="M_AXI_GP0_ARVALID"/>
            <PORTMAP LOGICAL="AWVALID" PHYSICAL="M_AXI_GP0_AWVALID"/>
            <PORTMAP LOGICAL="BREADY" PHYSICAL="M_AXI_GP0_BREADY"/>
            <PORTMAP LOGICAL="RREADY" PHYSICAL="M_AXI_GP0_RREADY"/>
            <PORTMAP LOGICAL="WLAST" PHYSICAL="M_AXI_GP0_WLAST"/>
            <PORTMAP LOGICAL="WVALID" PHYSICAL="M_AXI_GP0_WVALID"/>
            <PORTMAP LOGICAL="ARID" PHYSICAL="M_AXI_GP0_ARID"/>
            <PORTMAP LOGICAL="AWID" PHYSICAL="M_AXI_GP0_AWID"/>
            <PORTMAP LOGICAL="WID" PHYSICAL="M_AXI_GP0_WID"/>
            <PORTMAP LOGICAL="ARBURST" PHYSICAL="M_AXI_GP0_ARBURST"/>
            <PORTMAP LOGICAL="ARLOCK" PHYSICAL="M_AXI_GP0_ARLOCK"/>
            <PORTMAP LOGICAL="ARSIZE" PHYSICAL="M_AXI_GP0_ARSIZE"/>
            <PORTMAP LOGICAL="AWBURST" PHYSICAL="M_AXI_GP0_AWBURST"/>
            <PORTMAP LOGICAL="AWLOCK" PHYSICAL="M_AXI_GP0_AWLOCK"/>
            <PORTMAP LOGICAL="AWSIZE" PHYSICAL="M_AXI_GP0_AWSIZE"/>
            <PORTMAP LOGICAL="ARPROT" PHYSICAL="M_AXI_GP0_ARPROT"/>
            <PORTMAP LOGICAL="AWPROT" PHYSICAL="M_AXI_GP0_AWPROT"/>
            <PORTMAP LOGICAL="ARADDR" PHYSICAL="M_AXI_GP0_ARADDR"/>
            <PORTMAP LOGICAL="AWADDR" PHYSICAL="M_AXI_GP0_AWADDR"/>
            <PORTMAP LOGICAL="WDATA" PHYSICAL="M_AXI_GP0_WDATA"/>
            <PORTMAP LOGICAL="ARCACHE" PHYSICAL="M_AXI_GP0_ARCACHE"/>
            <PORTMAP LOGICAL="ARLEN" PHYSICAL="M_AXI_GP0_ARLEN"/>
            <PORTMAP LOGICAL="ARQOS" PHYSICAL="M_AXI_GP0_ARQOS"/>
            <PORTMAP LOGICAL="AWCACHE" PHYSICAL="M_AXI_GP0_AWCACHE"/>
            <PORTMAP LOGICAL="AWLEN" PHYSICAL="M_AXI_GP0_AWLEN"/>
            <PORTMAP LOGICAL="AWQOS" PHYSICAL="M_AXI_GP0_AWQOS"/>
            <PORTMAP LOGICAL="WSTRB" PHYSICAL="M_AXI_GP0_WSTRB"/>
            <PORTMAP LOGICAL="ARREADY" PHYSICAL="M_AXI_GP0_ARREADY"/>
            <PORTMAP LOGICAL="AWREADY" PHYSICAL="M_AXI_GP0_AWREADY"/>
            <PORTMAP LOGICAL="BVALID" PHYSICAL="M_AXI_GP0_BVALID"/>
            <PORTMAP LOGICAL="RLAST" PHYSICAL="M_AXI_GP0_RLAST"/>
            <PORTMAP LOGICAL="RVALID" PHYSICAL="M_AXI_GP0_RVALID"/>
            <PORTMAP LOGICAL="WREADY" PHYSICAL="M_AXI_GP0_WREADY"/>
            <PORTMAP LOGICAL="BID" PHYSICAL="M_AXI_GP0_BID"/>
            <PORTMAP LOGICAL="RID" PHYSICAL="M_AXI_GP0_RID"/>
            <PORTMAP LOGICAL="BRESP" PHYSICAL="M_AXI_GP0_BRESP"/>
            <PORTMAP LOGICAL="RRESP" PHYSICAL="M_AXI_GP0_RRESP"/>
            <PORTMAP LOGICAL="RDATA" PHYSICAL="M_AXI_GP0_RDATA"/>
          </PORTMAPS>
        </BUSINTERFACE>
        <BUSINTERFACE BUSNAME="writer_0_m_axi" DATAWIDTH="64" NAME="S_AXI_ACP" TYPE="SLAVE" VLNV="xilinx.com:interface:aximm:1.0">
          <PARAMETER NAME="NUM_WRITE_OUTSTANDING" VALUE="8"/>
          <PARAMETER NAME="NUM_READ_OUTSTANDING" VALUE="8"/>
          <PARAMETER NAME="DATA_WIDTH" VALUE="64"/>
          <PARAMETER NAME="PROTOCOL" VALUE="AXI3"/>
          <PARAMETER NAME="FREQ_HZ" VALUE="122880000"/>
          <PARAMETER NAME="ID_WIDTH" VALUE="3"/>
          <PARAMETER NAME="ADDR_WIDTH" VALUE="32"/>
          <PARAMETER NAME="AWUSER_WIDTH" VALUE="5"/>
          <PARAMETER NAME="ARUSER_WIDTH" VALUE="5"/>
          <PARAMETER NAME="WUSER_WIDTH" VALUE="0"/>
          <PARAMETER NAME="RUSER_WIDTH" VALUE="0"/>
          <PARAMETER NAME="BUSER_WIDTH" VALUE="0"/>
          <PARAMETER NAME="READ_WRITE_MODE" VALUE="READ_WRITE"/>
          <PARAMETER NAME="HAS_BURST" VALUE="1"/>
          <PARAMETER NAME="HAS_LOCK" VALUE="1"/>
          <PARAMETER NAME="HAS_PROT" VALUE="1"/>
          <PARAMETER NAME="HAS_CACHE" VALUE="1"/>
          <PARAMETER NAME="HAS_QOS" VALUE="1"/>
          <PARAMETER NAME="HAS_REGION" VALUE="0"/>
          <PARAMETER NAME="HAS_WSTRB" VALUE="1"/>
          <PARAMETER NAME="HAS_BRESP" VALUE="1"/>
          <PARAMETER NAME="HAS_RRESP" VALUE="1"/>
          <PARAMETER NAME="SUPPORTS_NARROW_BURST" VALUE="1"/>
          <PARAMETER NAME="MAX_BURST_LENGTH" VALUE="16"/>
          <PARAMETER NAME="PHASE" VALUE="0.0"/>
          <PARAMETER NAME="CLK_DOMAIN" VALUE="system_pll_0_0_clk_out1"/>
          <PARAMETER NAME="NUM_READ_THREADS" VALUE="1"/>
          <PARAMETER NAME="NUM_WRITE_THREADS" VALUE="1"/>
          <PARAMETER NAME="RUSER_BITS_PER_BYTE" VALUE="0"/>
          <PARAMETER NAME="WUSER_BITS_PER_BYTE" VALUE="0"/>
          <PARAMETER NAME="INSERT_VIP" VALUE="0"/>
          <PORTMAPS>
            <PORTMAP LOGICAL="ARREADY" PHYSICAL="S_AXI_ACP_ARREADY"/>
            <PORTMAP LOGICAL="AWREADY" PHYSICAL="S_AXI_ACP_AWREADY"/>
            <PORTMAP LOGICAL="BVALID" PHYSICAL="S_AXI_ACP_BVALID"/>
            <PORTMAP LOGICAL="RLAST" PHYSICAL="S_AXI_ACP_RLAST"/>
            <PORTMAP LOGICAL="RVALID" PHYSICAL="S_AXI_ACP_RVALID"/>
            <PORTMAP LOGICAL="WREADY" PHYSICAL="S_AXI_ACP_WREADY"/>
            <PORTMAP LOGICAL="BRESP" PHYSICAL="S_AXI_ACP_BRESP"/>
            <PORTMAP LOGICAL="RRESP" PHYSICAL="S_AXI_ACP_RRESP"/>
            <PORTMAP LOGICAL="BID" PHYSICAL="S_AXI_ACP_BID"/>
            <PORTMAP LOGICAL="RID" PHYSICAL="S_AXI_ACP_RID"/>
            <PORTMAP LOGICAL="RDATA" PHYSICAL="S_AXI_ACP_RDATA"/>
            <PORTMAP LOGICAL="ARVALID" PHYSICAL="S_AXI_ACP_ARVALID"/>
            <PORTMAP LOGICAL="AWVALID" PHYSICAL="S_AXI_ACP_AWVALID"/>
            <PORTMAP LOGICAL="BREADY" PHYSICAL="S_AXI_ACP_BREADY"/>
            <PORTMAP LOGICAL="RREADY" PHYSICAL="S_AXI_ACP_RREADY"/>
            <PORTMAP LOGICAL="WLAST" PHYSICAL="S_AXI_ACP_WLAST"/>
            <PORTMAP LOGICAL="WVALID" PHYSICAL="S_AXI_ACP_WVALID"/>
            <PORTMAP LOGICAL="ARID" PHYSICAL="S_AXI_ACP_ARID"/>
            <PORTMAP LOGICAL="ARPROT" PHYSICAL="S_AXI_ACP_ARPROT"/>
            <PORTMAP LOGICAL="AWID" PHYSICAL="S_AXI_ACP_AWID"/>
            <PORTMAP LOGICAL="AWPROT" PHYSICAL="S_AXI_ACP_AWPROT"/>
            <PORTMAP LOGICAL="WID" PHYSICAL="S_AXI_ACP_WID"/>
            <PORTMAP LOGICAL="ARADDR" PHYSICAL="S_AXI_ACP_ARADDR"/>
            <PORTMAP LOGICAL="AWADDR" PHYSICAL="S_AXI_ACP_AWADDR"/>
            <PORTMAP LOGICAL="ARCACHE" PHYSICAL="S_AXI_ACP_ARCACHE"/>
            <PORTMAP LOGICAL="ARLEN" PHYSICAL="S_AXI_ACP_ARLEN"/>
            <PORTMAP LOGICAL="ARQOS" PHYSICAL="S_AXI_ACP_ARQOS"/>
            <PORTMAP LOGICAL="AWCACHE" PHYSICAL="S_AXI_ACP_AWCACHE"/>
            <PORTMAP LOGICAL="AWLEN" PHYSICAL="S_AXI_ACP_AWLEN"/>
            <PORTMAP LOGICAL="AWQOS" PHYSICAL="S_AXI_ACP_AWQOS"/>
            <PORTMAP LOGICAL="ARBURST" PHYSICAL="S_AXI_ACP_ARBURST"/>
            <PORTMAP LOGICAL="ARLOCK" PHYSICAL="S_AXI_ACP_ARLOCK"/>
            <PORTMAP LOGICAL="ARSIZE" PHYSICAL="S_AXI_ACP_ARSIZE"/>
            <PORTMAP LOGICAL="AWBURST" PHYSICAL="S_AXI_ACP_AWBURST"/>
            <PORTMAP LOGICAL="AWLOCK" PHYSICAL="S_AXI_ACP_AWLOCK"/>
            <PORTMAP LOGICAL="AWSIZE" PHYSICAL="S_AXI_ACP_AWSIZE"/>
            <PORTMAP LOGICAL="ARUSER" PHYSICAL="S_AXI_ACP_ARUSER"/>
            <PORTMAP LOGICAL="AWUSER" PHYSICAL="S_AXI_ACP_AWUSER"/>
            <PORTMAP LOGICAL="WDATA" PHYSICAL="S_AXI_ACP_WDATA"/>
            <PORTMAP LOGICAL="WSTRB" PHYSICAL="S_AXI_ACP_WSTRB"/>
          </PORTMAPS>
        </BUSINTERFACE>
      </BUSINTERFACES>
      <MEMORYMAP/>
      <PERIPHERALS>
        <PERIPHERAL INSTANCE="hub_0"/>
      </PERIPHERALS>
    </MODULE>
    <MODULE COREREVISION="1" FULLNAME="/rate_0" HWVERSION="1.0" INSTANCE="rate_0" IPTYPE="PERIPHERAL" IS_ENABLE="1" MODCLASS="PERIPHERAL" MODTYPE="axis_variable" VLNV="pavel-demin:user:axis_variable:1.0">
      <DOCUMENTS/>
      <PARAMETERS>
        <PARAMETER NAME="AXIS_TDATA_WIDTH" VALUE="16"/>
        <PARAMETER NAME="Component_Name" VALUE="system_rate_0_0"/>
        <PARAMETER NAME="EDK_IPTYPE" VALUE="PERIPHERAL"/>
      </PARAMETERS>
      <PORTS>
        <PORT CLKFREQUENCY="122880000" DIR="I" NAME="aclk" SIGIS="clk" SIGNAME="pll_0_clk_out1">
          <CONNECTIONS>
            <CONNECTION INSTANCE="pll_0" PORT="clk_out1"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" NAME="aresetn" POLARITY="ACTIVE_LOW" SIGIS="rst" SIGNAME="slice_0_dout">
          <CONNECTIONS>
            <CONNECTION INSTANCE="slice_0" PORT="dout"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" LEFT="15" NAME="cfg_data" RIGHT="0" SIGIS="undef" SIGNAME="slice_2_dout">
          <CONNECTIONS>
            <CONNECTION INSTANCE="slice_2" PORT="dout"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" NAME="m_axis_tready" SIGIS="undef" SIGNAME="cic_0_s_axis_config_tready">
          <CONNECTIONS>
            <CONNECTION INSTANCE="cic_0" PORT="s_axis_config_tready"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" LEFT="15" NAME="m_axis_tdata" RIGHT="0" SIGIS="undef" SIGNAME="cic_0_s_axis_config_tdata">
          <CONNECTIONS>
            <CONNECTION INSTANCE="cic_0" PORT="s_axis_config_tdata"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" NAME="m_axis_tvalid" SIGIS="undef" SIGNAME="cic_0_s_axis_config_tvalid">
          <CONNECTIONS>
            <CONNECTION INSTANCE="cic_0" PORT="s_axis_config_tvalid"/>
          </CONNECTIONS>
        </PORT>
      </PORTS>
      <BUSINTERFACES>
        <BUSINTERFACE BUSNAME="rate_0_m_axis" NAME="m_axis" TYPE="INITIATOR" VLNV="xilinx.com:interface:axis:1.0">
          <PARAMETER NAME="TDATA_NUM_BYTES" VALUE="2"/>
          <PARAMETER NAME="TDEST_WIDTH" VALUE="0"/>
          <PARAMETER NAME="TID_WIDTH" VALUE="0"/>
          <PARAMETER NAME="TUSER_WIDTH" VALUE="0"/>
          <PARAMETER NAME="HAS_TREADY" VALUE="1"/>
          <PARAMETER NAME="HAS_TSTRB" VALUE="0"/>
          <PARAMETER NAME="HAS_TKEEP" VALUE="0"/>
          <PARAMETER NAME="HAS_TLAST" VALUE="0"/>
          <PARAMETER NAME="FREQ_HZ" VALUE="122880000"/>
          <PARAMETER NAME="PHASE" VALUE="0.0"/>
          <PARAMETER NAME="CLK_DOMAIN" VALUE="system_pll_0_0_clk_out1"/>
          <PARAMETER NAME="LAYERED_METADATA" VALUE="undef"/>
          <PARAMETER NAME="INSERT_VIP" VALUE="0"/>
          <PORTMAPS>
            <PORTMAP LOGICAL="TDATA" PHYSICAL="m_axis_tdata"/>
            <PORTMAP LOGICAL="TVALID" PHYSICAL="m_axis_tvalid"/>
            <PORTMAP LOGICAL="TREADY" PHYSICAL="m_axis_tready"/>
          </PORTMAPS>
        </BUSINTERFACE>
      </BUSINTERFACES>
    </MODULE>
    <MODULE COREREVISION="1" FULLNAME="/rate_1" HWVERSION="1.0" INSTANCE="rate_1" IPTYPE="PERIPHERAL" IS_ENABLE="1" MODCLASS="PERIPHERAL" MODTYPE="axis_variable" VLNV="pavel-demin:user:axis_variable:1.0">
      <DOCUMENTS/>
      <PARAMETERS>
        <PARAMETER NAME="AXIS_TDATA_WIDTH" VALUE="16"/>
        <PARAMETER NAME="Component_Name" VALUE="system_rate_1_0"/>
        <PARAMETER NAME="EDK_IPTYPE" VALUE="PERIPHERAL"/>
      </PARAMETERS>
      <PORTS>
        <PORT CLKFREQUENCY="122880000" DIR="I" NAME="aclk" SIGIS="clk" SIGNAME="pll_0_clk_out1">
          <CONNECTIONS>
            <CONNECTION INSTANCE="pll_0" PORT="clk_out1"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" NAME="aresetn" POLARITY="ACTIVE_LOW" SIGIS="rst" SIGNAME="slice_0_dout">
          <CONNECTIONS>
            <CONNECTION INSTANCE="slice_0" PORT="dout"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" LEFT="15" NAME="cfg_data" RIGHT="0" SIGIS="undef" SIGNAME="slice_2_dout">
          <CONNECTIONS>
            <CONNECTION INSTANCE="slice_2" PORT="dout"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" NAME="m_axis_tready" SIGIS="undef" SIGNAME="cic_1_s_axis_config_tready">
          <CONNECTIONS>
            <CONNECTION INSTANCE="cic_1" PORT="s_axis_config_tready"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" LEFT="15" NAME="m_axis_tdata" RIGHT="0" SIGIS="undef" SIGNAME="cic_1_s_axis_config_tdata">
          <CONNECTIONS>
            <CONNECTION INSTANCE="cic_1" PORT="s_axis_config_tdata"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" NAME="m_axis_tvalid" SIGIS="undef" SIGNAME="cic_1_s_axis_config_tvalid">
          <CONNECTIONS>
            <CONNECTION INSTANCE="cic_1" PORT="s_axis_config_tvalid"/>
          </CONNECTIONS>
        </PORT>
      </PORTS>
      <BUSINTERFACES>
        <BUSINTERFACE BUSNAME="rate_1_m_axis" NAME="m_axis" TYPE="INITIATOR" VLNV="xilinx.com:interface:axis:1.0">
          <PARAMETER NAME="TDATA_NUM_BYTES" VALUE="2"/>
          <PARAMETER NAME="TDEST_WIDTH" VALUE="0"/>
          <PARAMETER NAME="TID_WIDTH" VALUE="0"/>
          <PARAMETER NAME="TUSER_WIDTH" VALUE="0"/>
          <PARAMETER NAME="HAS_TREADY" VALUE="1"/>
          <PARAMETER NAME="HAS_TSTRB" VALUE="0"/>
          <PARAMETER NAME="HAS_TKEEP" VALUE="0"/>
          <PARAMETER NAME="HAS_TLAST" VALUE="0"/>
          <PARAMETER NAME="FREQ_HZ" VALUE="122880000"/>
          <PARAMETER NAME="PHASE" VALUE="0.0"/>
          <PARAMETER NAME="CLK_DOMAIN" VALUE="system_pll_0_0_clk_out1"/>
          <PARAMETER NAME="LAYERED_METADATA" VALUE="undef"/>
          <PARAMETER NAME="INSERT_VIP" VALUE="0"/>
          <PORTMAPS>
            <PORTMAP LOGICAL="TDATA" PHYSICAL="m_axis_tdata"/>
            <PORTMAP LOGICAL="TVALID" PHYSICAL="m_axis_tvalid"/>
            <PORTMAP LOGICAL="TREADY" PHYSICAL="m_axis_tready"/>
          </PORTMAPS>
        </BUSINTERFACE>
      </BUSINTERFACES>
    </MODULE>
    <MODULE COREREVISION="1" FULLNAME="/rate_2" HWVERSION="1.0" INSTANCE="rate_2" IPTYPE="PERIPHERAL" IS_ENABLE="1" MODCLASS="PERIPHERAL" MODTYPE="axis_variable" VLNV="pavel-demin:user:axis_variable:1.0">
      <DOCUMENTS/>
      <PARAMETERS>
        <PARAMETER NAME="AXIS_TDATA_WIDTH" VALUE="16"/>
        <PARAMETER NAME="Component_Name" VALUE="system_rate_2_0"/>
        <PARAMETER NAME="EDK_IPTYPE" VALUE="PERIPHERAL"/>
      </PARAMETERS>
      <PORTS>
        <PORT CLKFREQUENCY="122880000" DIR="I" NAME="aclk" SIGIS="clk" SIGNAME="pll_0_clk_out1">
          <CONNECTIONS>
            <CONNECTION INSTANCE="pll_0" PORT="clk_out1"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" NAME="aresetn" POLARITY="ACTIVE_LOW" SIGIS="rst" SIGNAME="slice_0_dout">
          <CONNECTIONS>
            <CONNECTION INSTANCE="slice_0" PORT="dout"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" LEFT="15" NAME="cfg_data" RIGHT="0" SIGIS="undef" SIGNAME="slice_2_dout">
          <CONNECTIONS>
            <CONNECTION INSTANCE="slice_2" PORT="dout"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" NAME="m_axis_tready" SIGIS="undef" SIGNAME="cic_2_s_axis_config_tready">
          <CONNECTIONS>
            <CONNECTION INSTANCE="cic_2" PORT="s_axis_config_tready"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" LEFT="15" NAME="m_axis_tdata" RIGHT="0" SIGIS="undef" SIGNAME="cic_2_s_axis_config_tdata">
          <CONNECTIONS>
            <CONNECTION INSTANCE="cic_2" PORT="s_axis_config_tdata"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" NAME="m_axis_tvalid" SIGIS="undef" SIGNAME="cic_2_s_axis_config_tvalid">
          <CONNECTIONS>
            <CONNECTION INSTANCE="cic_2" PORT="s_axis_config_tvalid"/>
          </CONNECTIONS>
        </PORT>
      </PORTS>
      <BUSINTERFACES>
        <BUSINTERFACE BUSNAME="rate_2_m_axis" NAME="m_axis" TYPE="INITIATOR" VLNV="xilinx.com:interface:axis:1.0">
          <PARAMETER NAME="TDATA_NUM_BYTES" VALUE="2"/>
          <PARAMETER NAME="TDEST_WIDTH" VALUE="0"/>
          <PARAMETER NAME="TID_WIDTH" VALUE="0"/>
          <PARAMETER NAME="TUSER_WIDTH" VALUE="0"/>
          <PARAMETER NAME="HAS_TREADY" VALUE="1"/>
          <PARAMETER NAME="HAS_TSTRB" VALUE="0"/>
          <PARAMETER NAME="HAS_TKEEP" VALUE="0"/>
          <PARAMETER NAME="HAS_TLAST" VALUE="0"/>
          <PARAMETER NAME="FREQ_HZ" VALUE="122880000"/>
          <PARAMETER NAME="PHASE" VALUE="0.0"/>
          <PARAMETER NAME="CLK_DOMAIN" VALUE="system_pll_0_0_clk_out1"/>
          <PARAMETER NAME="LAYERED_METADATA" VALUE="undef"/>
          <PARAMETER NAME="INSERT_VIP" VALUE="0"/>
          <PORTMAPS>
            <PORTMAP LOGICAL="TDATA" PHYSICAL="m_axis_tdata"/>
            <PORTMAP LOGICAL="TVALID" PHYSICAL="m_axis_tvalid"/>
            <PORTMAP LOGICAL="TREADY" PHYSICAL="m_axis_tready"/>
          </PORTMAPS>
        </BUSINTERFACE>
      </BUSINTERFACES>
    </MODULE>
    <MODULE COREREVISION="1" FULLNAME="/rate_3" HWVERSION="1.0" INSTANCE="rate_3" IPTYPE="PERIPHERAL" IS_ENABLE="1" MODCLASS="PERIPHERAL" MODTYPE="axis_variable" VLNV="pavel-demin:user:axis_variable:1.0">
      <DOCUMENTS/>
      <PARAMETERS>
        <PARAMETER NAME="AXIS_TDATA_WIDTH" VALUE="16"/>
        <PARAMETER NAME="Component_Name" VALUE="system_rate_3_0"/>
        <PARAMETER NAME="EDK_IPTYPE" VALUE="PERIPHERAL"/>
      </PARAMETERS>
      <PORTS>
        <PORT CLKFREQUENCY="122880000" DIR="I" NAME="aclk" SIGIS="clk" SIGNAME="pll_0_clk_out1">
          <CONNECTIONS>
            <CONNECTION INSTANCE="pll_0" PORT="clk_out1"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" NAME="aresetn" POLARITY="ACTIVE_LOW" SIGIS="rst" SIGNAME="slice_0_dout">
          <CONNECTIONS>
            <CONNECTION INSTANCE="slice_0" PORT="dout"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" LEFT="15" NAME="cfg_data" RIGHT="0" SIGIS="undef" SIGNAME="slice_2_dout">
          <CONNECTIONS>
            <CONNECTION INSTANCE="slice_2" PORT="dout"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" NAME="m_axis_tready" SIGIS="undef" SIGNAME="cic_3_s_axis_config_tready">
          <CONNECTIONS>
            <CONNECTION INSTANCE="cic_3" PORT="s_axis_config_tready"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" LEFT="15" NAME="m_axis_tdata" RIGHT="0" SIGIS="undef" SIGNAME="cic_3_s_axis_config_tdata">
          <CONNECTIONS>
            <CONNECTION INSTANCE="cic_3" PORT="s_axis_config_tdata"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" NAME="m_axis_tvalid" SIGIS="undef" SIGNAME="cic_3_s_axis_config_tvalid">
          <CONNECTIONS>
            <CONNECTION INSTANCE="cic_3" PORT="s_axis_config_tvalid"/>
          </CONNECTIONS>
        </PORT>
      </PORTS>
      <BUSINTERFACES>
        <BUSINTERFACE BUSNAME="rate_3_m_axis" NAME="m_axis" TYPE="INITIATOR" VLNV="xilinx.com:interface:axis:1.0">
          <PARAMETER NAME="TDATA_NUM_BYTES" VALUE="2"/>
          <PARAMETER NAME="TDEST_WIDTH" VALUE="0"/>
          <PARAMETER NAME="TID_WIDTH" VALUE="0"/>
          <PARAMETER NAME="TUSER_WIDTH" VALUE="0"/>
          <PARAMETER NAME="HAS_TREADY" VALUE="1"/>
          <PARAMETER NAME="HAS_TSTRB" VALUE="0"/>
          <PARAMETER NAME="HAS_TKEEP" VALUE="0"/>
          <PARAMETER NAME="HAS_TLAST" VALUE="0"/>
          <PARAMETER NAME="FREQ_HZ" VALUE="122880000"/>
          <PARAMETER NAME="PHASE" VALUE="0.0"/>
          <PARAMETER NAME="CLK_DOMAIN" VALUE="system_pll_0_0_clk_out1"/>
          <PARAMETER NAME="LAYERED_METADATA" VALUE="undef"/>
          <PARAMETER NAME="INSERT_VIP" VALUE="0"/>
          <PORTMAPS>
            <PORTMAP LOGICAL="TDATA" PHYSICAL="m_axis_tdata"/>
            <PORTMAP LOGICAL="TVALID" PHYSICAL="m_axis_tvalid"/>
            <PORTMAP LOGICAL="TREADY" PHYSICAL="m_axis_tready"/>
          </PORTMAPS>
        </BUSINTERFACE>
      </BUSINTERFACES>
    </MODULE>
    <MODULE COREREVISION="13" FULLNAME="/rst_0" HWVERSION="5.0" INSTANCE="rst_0" IPTYPE="PERIPHERAL" IS_ENABLE="1" MODCLASS="PERIPHERAL" MODTYPE="proc_sys_reset" VLNV="xilinx.com:ip:proc_sys_reset:5.0">
      <DOCUMENTS>
        <DOCUMENT SOURCE="http://www.xilinx.com/cgi-bin/docs/ipdoc?c=proc_sys_reset;v=v5_0;d=pg164-proc-sys-reset.pdf"/>
      </DOCUMENTS>
      <PARAMETERS>
        <PARAMETER NAME="C_FAMILY" VALUE="zynq"/>
        <PARAMETER NAME="C_EXT_RST_WIDTH" VALUE="4"/>
        <PARAMETER NAME="C_AUX_RST_WIDTH" VALUE="4"/>
        <PARAMETER NAME="C_EXT_RESET_HIGH" VALUE="0"/>
        <PARAMETER NAME="C_AUX_RESET_HIGH" VALUE="0"/>
        <PARAMETER NAME="C_NUM_BUS_RST" VALUE="1"/>
        <PARAMETER NAME="C_NUM_PERP_RST" VALUE="1"/>
        <PARAMETER NAME="C_NUM_INTERCONNECT_ARESETN" VALUE="1"/>
        <PARAMETER NAME="C_NUM_PERP_ARESETN" VALUE="1"/>
        <PARAMETER NAME="Component_Name" VALUE="system_rst_0_0"/>
        <PARAMETER NAME="USE_BOARD_FLOW" VALUE="false"/>
        <PARAMETER NAME="RESET_BOARD_INTERFACE" VALUE="Custom"/>
        <PARAMETER NAME="EDK_IPTYPE" VALUE="PERIPHERAL"/>
      </PARAMETERS>
      <PORTS>
        <PORT CLKFREQUENCY="122880000" DIR="I" NAME="slowest_sync_clk" SIGIS="clk" SIGNAME="pll_0_clk_out1">
          <CONNECTIONS>
            <CONNECTION INSTANCE="pll_0" PORT="clk_out1"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" NAME="ext_reset_in" POLARITY="ACTIVE_LOW" SIGIS="rst" SIGNAME="const_0_dout">
          <CONNECTIONS>
            <CONNECTION INSTANCE="const_0" PORT="dout"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" NAME="aux_reset_in" POLARITY="ACTIVE_LOW" SIGIS="rst"/>
        <PORT DIR="I" NAME="mb_debug_sys_rst" POLARITY="ACTIVE_HIGH" SIGIS="rst"/>
        <PORT DIR="I" NAME="dcm_locked" SIGIS="undef" SIGNAME="pll_0_locked">
          <CONNECTIONS>
            <CONNECTION INSTANCE="pll_0" PORT="locked"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" NAME="mb_reset" POLARITY="ACTIVE_HIGH" SIGIS="rst"/>
        <PORT DIR="O" LEFT="0" NAME="bus_struct_reset" POLARITY="ACTIVE_HIGH" RIGHT="0" SIGIS="rst"/>
        <PORT DIR="O" LEFT="0" NAME="peripheral_reset" POLARITY="ACTIVE_HIGH" RIGHT="0" SIGIS="rst"/>
        <PORT DIR="O" LEFT="0" NAME="interconnect_aresetn" POLARITY="ACTIVE_LOW" RIGHT="0" SIGIS="rst"/>
        <PORT DIR="O" LEFT="0" NAME="peripheral_aresetn" POLARITY="ACTIVE_LOW" RIGHT="0" SIGIS="rst" SIGNAME="rst_0_peripheral_aresetn">
          <CONNECTIONS>
            <CONNECTION INSTANCE="hub_0" PORT="aresetn"/>
            <CONNECTION INSTANCE="dds_0" PORT="aresetn"/>
            <CONNECTION INSTANCE="dds_1" PORT="aresetn"/>
            <CONNECTION INSTANCE="dds_2" PORT="aresetn"/>
            <CONNECTION INSTANCE="dds_3" PORT="aresetn"/>
          </CONNECTIONS>
        </PORT>
      </PORTS>
      <BUSINTERFACES/>
    </MODULE>
    <MODULE COREREVISION="1" FULLNAME="/slice_0" HWVERSION="1.0" INSTANCE="slice_0" IPTYPE="PERIPHERAL" IS_ENABLE="1" MODCLASS="PERIPHERAL" MODTYPE="port_slicer" VLNV="pavel-demin:user:port_slicer:1.0">
      <DOCUMENTS/>
      <PARAMETERS>
        <PARAMETER NAME="DIN_WIDTH" VALUE="224"/>
        <PARAMETER NAME="DIN_FROM" VALUE="0"/>
        <PARAMETER NAME="DIN_TO" VALUE="0"/>
        <PARAMETER NAME="Component_Name" VALUE="system_slice_0_0"/>
        <PARAMETER NAME="EDK_IPTYPE" VALUE="PERIPHERAL"/>
      </PARAMETERS>
      <PORTS>
        <PORT DIR="I" LEFT="223" NAME="din" RIGHT="0" SIGIS="undef" SIGNAME="hub_0_cfg_data">
          <CONNECTIONS>
            <CONNECTION INSTANCE="hub_0" PORT="cfg_data"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" LEFT="0" NAME="dout" RIGHT="0" SIGIS="undef" SIGNAME="slice_0_dout">
          <CONNECTIONS>
            <CONNECTION INSTANCE="rate_0" PORT="aresetn"/>
            <CONNECTION INSTANCE="cic_0" PORT="aresetn"/>
            <CONNECTION INSTANCE="rate_1" PORT="aresetn"/>
            <CONNECTION INSTANCE="cic_1" PORT="aresetn"/>
            <CONNECTION INSTANCE="rate_2" PORT="aresetn"/>
            <CONNECTION INSTANCE="cic_2" PORT="aresetn"/>
            <CONNECTION INSTANCE="rate_3" PORT="aresetn"/>
            <CONNECTION INSTANCE="cic_3" PORT="aresetn"/>
            <CONNECTION INSTANCE="comb_0" PORT="aresetn"/>
            <CONNECTION INSTANCE="fir_0" PORT="aresetn"/>
            <CONNECTION INSTANCE="subset_0" PORT="aresetn"/>
          </CONNECTIONS>
        </PORT>
      </PORTS>
      <BUSINTERFACES/>
    </MODULE>
    <MODULE COREREVISION="1" FULLNAME="/slice_1" HWVERSION="1.0" INSTANCE="slice_1" IPTYPE="PERIPHERAL" IS_ENABLE="1" MODCLASS="PERIPHERAL" MODTYPE="port_slicer" VLNV="pavel-demin:user:port_slicer:1.0">
      <DOCUMENTS/>
      <PARAMETERS>
        <PARAMETER NAME="DIN_WIDTH" VALUE="224"/>
        <PARAMETER NAME="DIN_FROM" VALUE="1"/>
        <PARAMETER NAME="DIN_TO" VALUE="1"/>
        <PARAMETER NAME="Component_Name" VALUE="system_slice_1_0"/>
        <PARAMETER NAME="EDK_IPTYPE" VALUE="PERIPHERAL"/>
      </PARAMETERS>
      <PORTS>
        <PORT DIR="I" LEFT="223" NAME="din" RIGHT="0" SIGIS="undef" SIGNAME="hub_0_cfg_data">
          <CONNECTIONS>
            <CONNECTION INSTANCE="hub_0" PORT="cfg_data"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" LEFT="0" NAME="dout" RIGHT="0" SIGIS="undef" SIGNAME="slice_1_dout">
          <CONNECTIONS>
            <CONNECTION INSTANCE="writer_0" PORT="aresetn"/>
            <CONNECTION INSTANCE="fsk_detector_1_00_0" PORT="aresetn"/>
          </CONNECTIONS>
        </PORT>
      </PORTS>
      <BUSINTERFACES/>
    </MODULE>
    <MODULE COREREVISION="1" FULLNAME="/slice_2" HWVERSION="1.0" INSTANCE="slice_2" IPTYPE="PERIPHERAL" IS_ENABLE="1" MODCLASS="PERIPHERAL" MODTYPE="port_slicer" VLNV="pavel-demin:user:port_slicer:1.0">
      <DOCUMENTS/>
      <PARAMETERS>
        <PARAMETER NAME="DIN_WIDTH" VALUE="224"/>
        <PARAMETER NAME="DIN_FROM" VALUE="31"/>
        <PARAMETER NAME="DIN_TO" VALUE="16"/>
        <PARAMETER NAME="Component_Name" VALUE="system_slice_2_0"/>
        <PARAMETER NAME="EDK_IPTYPE" VALUE="PERIPHERAL"/>
      </PARAMETERS>
      <PORTS>
        <PORT DIR="I" LEFT="223" NAME="din" RIGHT="0" SIGIS="undef" SIGNAME="hub_0_cfg_data">
          <CONNECTIONS>
            <CONNECTION INSTANCE="hub_0" PORT="cfg_data"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" LEFT="15" NAME="dout" RIGHT="0" SIGIS="undef" SIGNAME="slice_2_dout">
          <CONNECTIONS>
            <CONNECTION INSTANCE="rate_0" PORT="cfg_data"/>
            <CONNECTION INSTANCE="rate_1" PORT="cfg_data"/>
            <CONNECTION INSTANCE="rate_2" PORT="cfg_data"/>
            <CONNECTION INSTANCE="rate_3" PORT="cfg_data"/>
          </CONNECTIONS>
        </PORT>
      </PORTS>
      <BUSINTERFACES/>
    </MODULE>
    <MODULE COREREVISION="1" FULLNAME="/slice_3" HWVERSION="1.0" INSTANCE="slice_3" IPTYPE="PERIPHERAL" IS_ENABLE="1" MODCLASS="PERIPHERAL" MODTYPE="port_slicer" VLNV="pavel-demin:user:port_slicer:1.0">
      <DOCUMENTS/>
      <PARAMETERS>
        <PARAMETER NAME="DIN_WIDTH" VALUE="224"/>
        <PARAMETER NAME="DIN_FROM" VALUE="63"/>
        <PARAMETER NAME="DIN_TO" VALUE="32"/>
        <PARAMETER NAME="Component_Name" VALUE="system_slice_3_0"/>
        <PARAMETER NAME="EDK_IPTYPE" VALUE="PERIPHERAL"/>
      </PARAMETERS>
      <PORTS>
        <PORT DIR="I" LEFT="223" NAME="din" RIGHT="0" SIGIS="undef" SIGNAME="hub_0_cfg_data">
          <CONNECTIONS>
            <CONNECTION INSTANCE="hub_0" PORT="cfg_data"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" LEFT="31" NAME="dout" RIGHT="0" SIGIS="undef" SIGNAME="slice_3_dout">
          <CONNECTIONS>
            <CONNECTION INSTANCE="writer_0" PORT="min_addr"/>
          </CONNECTIONS>
        </PORT>
      </PORTS>
      <BUSINTERFACES/>
    </MODULE>
    <MODULE COREREVISION="1" FULLNAME="/slice_4" HWVERSION="1.0" INSTANCE="slice_4" IPTYPE="PERIPHERAL" IS_ENABLE="1" MODCLASS="PERIPHERAL" MODTYPE="port_slicer" VLNV="pavel-demin:user:port_slicer:1.0">
      <DOCUMENTS/>
      <PARAMETERS>
        <PARAMETER NAME="DIN_WIDTH" VALUE="224"/>
        <PARAMETER NAME="DIN_FROM" VALUE="95"/>
        <PARAMETER NAME="DIN_TO" VALUE="64"/>
        <PARAMETER NAME="Component_Name" VALUE="system_slice_4_0"/>
        <PARAMETER NAME="EDK_IPTYPE" VALUE="PERIPHERAL"/>
      </PARAMETERS>
      <PORTS>
        <PORT DIR="I" LEFT="223" NAME="din" RIGHT="0" SIGIS="undef" SIGNAME="hub_0_cfg_data">
          <CONNECTIONS>
            <CONNECTION INSTANCE="hub_0" PORT="cfg_data"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" LEFT="31" NAME="dout" RIGHT="0" SIGIS="undef" SIGNAME="slice_4_dout">
          <CONNECTIONS>
            <CONNECTION INSTANCE="dds_0" PORT="pinc"/>
          </CONNECTIONS>
        </PORT>
      </PORTS>
      <BUSINTERFACES/>
    </MODULE>
    <MODULE COREREVISION="1" FULLNAME="/slice_5" HWVERSION="1.0" INSTANCE="slice_5" IPTYPE="PERIPHERAL" IS_ENABLE="1" MODCLASS="PERIPHERAL" MODTYPE="port_slicer" VLNV="pavel-demin:user:port_slicer:1.0">
      <DOCUMENTS/>
      <PARAMETERS>
        <PARAMETER NAME="DIN_WIDTH" VALUE="224"/>
        <PARAMETER NAME="DIN_FROM" VALUE="127"/>
        <PARAMETER NAME="DIN_TO" VALUE="96"/>
        <PARAMETER NAME="Component_Name" VALUE="system_slice_5_0"/>
        <PARAMETER NAME="EDK_IPTYPE" VALUE="PERIPHERAL"/>
      </PARAMETERS>
      <PORTS>
        <PORT DIR="I" LEFT="223" NAME="din" RIGHT="0" SIGIS="undef" SIGNAME="hub_0_cfg_data">
          <CONNECTIONS>
            <CONNECTION INSTANCE="hub_0" PORT="cfg_data"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" LEFT="31" NAME="dout" RIGHT="0" SIGIS="undef" SIGNAME="slice_5_dout">
          <CONNECTIONS>
            <CONNECTION INSTANCE="dds_1" PORT="pinc"/>
          </CONNECTIONS>
        </PORT>
      </PORTS>
      <BUSINTERFACES/>
    </MODULE>
    <MODULE COREREVISION="1" FULLNAME="/slice_6" HWVERSION="1.0" INSTANCE="slice_6" IPTYPE="PERIPHERAL" IS_ENABLE="1" MODCLASS="PERIPHERAL" MODTYPE="port_slicer" VLNV="pavel-demin:user:port_slicer:1.0">
      <DOCUMENTS/>
      <PARAMETERS>
        <PARAMETER NAME="DIN_WIDTH" VALUE="224"/>
        <PARAMETER NAME="DIN_FROM" VALUE="159"/>
        <PARAMETER NAME="DIN_TO" VALUE="128"/>
        <PARAMETER NAME="Component_Name" VALUE="system_slice_6_0"/>
        <PARAMETER NAME="EDK_IPTYPE" VALUE="PERIPHERAL"/>
      </PARAMETERS>
      <PORTS>
        <PORT DIR="I" LEFT="223" NAME="din" RIGHT="0" SIGIS="undef" SIGNAME="hub_0_cfg_data">
          <CONNECTIONS>
            <CONNECTION INSTANCE="hub_0" PORT="cfg_data"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" LEFT="31" NAME="dout" RIGHT="0" SIGIS="undef" SIGNAME="slice_6_dout">
          <CONNECTIONS>
            <CONNECTION INSTANCE="dds_2" PORT="pinc"/>
          </CONNECTIONS>
        </PORT>
      </PORTS>
      <BUSINTERFACES/>
    </MODULE>
    <MODULE COREREVISION="1" FULLNAME="/slice_7" HWVERSION="1.0" INSTANCE="slice_7" IPTYPE="PERIPHERAL" IS_ENABLE="1" MODCLASS="PERIPHERAL" MODTYPE="port_slicer" VLNV="pavel-demin:user:port_slicer:1.0">
      <DOCUMENTS/>
      <PARAMETERS>
        <PARAMETER NAME="DIN_WIDTH" VALUE="224"/>
        <PARAMETER NAME="DIN_FROM" VALUE="191"/>
        <PARAMETER NAME="DIN_TO" VALUE="160"/>
        <PARAMETER NAME="Component_Name" VALUE="system_slice_7_0"/>
        <PARAMETER NAME="EDK_IPTYPE" VALUE="PERIPHERAL"/>
      </PARAMETERS>
      <PORTS>
        <PORT DIR="I" LEFT="223" NAME="din" RIGHT="0" SIGIS="undef" SIGNAME="hub_0_cfg_data">
          <CONNECTIONS>
            <CONNECTION INSTANCE="hub_0" PORT="cfg_data"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" LEFT="31" NAME="dout" RIGHT="0" SIGIS="undef" SIGNAME="slice_7_dout">
          <CONNECTIONS>
            <CONNECTION INSTANCE="dds_3" PORT="pinc"/>
          </CONNECTIONS>
        </PORT>
      </PORTS>
      <BUSINTERFACES/>
    </MODULE>
    <MODULE COREREVISION="1" FULLNAME="/slice_8" HWVERSION="1.0" INSTANCE="slice_8" IPTYPE="PERIPHERAL" IS_ENABLE="1" MODCLASS="PERIPHERAL" MODTYPE="port_slicer" VLNV="pavel-demin:user:port_slicer:1.0">
      <DOCUMENTS/>
      <PARAMETERS>
        <PARAMETER NAME="DIN_WIDTH" VALUE="224"/>
        <PARAMETER NAME="DIN_FROM" VALUE="207"/>
        <PARAMETER NAME="DIN_TO" VALUE="192"/>
        <PARAMETER NAME="Component_Name" VALUE="system_slice_8_0"/>
        <PARAMETER NAME="EDK_IPTYPE" VALUE="PERIPHERAL"/>
      </PARAMETERS>
      <PORTS>
        <PORT DIR="I" LEFT="223" NAME="din" RIGHT="0" SIGIS="undef" SIGNAME="hub_0_cfg_data">
          <CONNECTIONS>
            <CONNECTION INSTANCE="hub_0" PORT="cfg_data"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" LEFT="15" NAME="dout" RIGHT="0" SIGIS="undef" SIGNAME="slice_8_dout">
          <CONNECTIONS>
            <CONNECTION INSTANCE="mult_4" PORT="B"/>
          </CONNECTIONS>
        </PORT>
      </PORTS>
      <BUSINTERFACES/>
    </MODULE>
    <MODULE COREREVISION="1" FULLNAME="/slice_9" HWVERSION="1.0" INSTANCE="slice_9" IPTYPE="PERIPHERAL" IS_ENABLE="1" MODCLASS="PERIPHERAL" MODTYPE="port_slicer" VLNV="pavel-demin:user:port_slicer:1.0">
      <DOCUMENTS/>
      <PARAMETERS>
        <PARAMETER NAME="DIN_WIDTH" VALUE="224"/>
        <PARAMETER NAME="DIN_FROM" VALUE="223"/>
        <PARAMETER NAME="DIN_TO" VALUE="208"/>
        <PARAMETER NAME="Component_Name" VALUE="system_slice_9_0"/>
        <PARAMETER NAME="EDK_IPTYPE" VALUE="PERIPHERAL"/>
      </PARAMETERS>
      <PORTS>
        <PORT DIR="I" LEFT="223" NAME="din" RIGHT="0" SIGIS="undef" SIGNAME="hub_0_cfg_data">
          <CONNECTIONS>
            <CONNECTION INSTANCE="hub_0" PORT="cfg_data"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" LEFT="15" NAME="dout" RIGHT="0" SIGIS="undef" SIGNAME="slice_9_dout">
          <CONNECTIONS>
            <CONNECTION INSTANCE="writer_0" PORT="cfg_data"/>
          </CONNECTIONS>
        </PORT>
      </PORTS>
      <BUSINTERFACES/>
    </MODULE>
    <MODULE COREREVISION="1" FULLNAME="/slice_GPIO_out" HWVERSION="1.0" INSTANCE="slice_GPIO_out" IPTYPE="PERIPHERAL" IS_ENABLE="1" MODCLASS="PERIPHERAL" MODTYPE="port_slicer" VLNV="pavel-demin:user:port_slicer:1.0">
      <DOCUMENTS/>
      <PARAMETERS>
        <PARAMETER NAME="DIN_WIDTH" VALUE="224"/>
        <PARAMETER NAME="DIN_FROM" VALUE="15"/>
        <PARAMETER NAME="DIN_TO" VALUE="8"/>
        <PARAMETER NAME="Component_Name" VALUE="system_slice_GPIO_out_0"/>
        <PARAMETER NAME="EDK_IPTYPE" VALUE="PERIPHERAL"/>
      </PARAMETERS>
      <PORTS>
        <PORT DIR="I" LEFT="223" NAME="din" RIGHT="0" SIGIS="undef" SIGNAME="hub_0_cfg_data">
          <CONNECTIONS>
            <CONNECTION INSTANCE="hub_0" PORT="cfg_data"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" LEFT="7" NAME="dout" RIGHT="0" SIGIS="undef"/>
      </PORTS>
      <BUSINTERFACES/>
    </MODULE>
    <MODULE COREREVISION="1" FULLNAME="/slice_GPIO_out1" HWVERSION="1.0" INSTANCE="slice_GPIO_out1" IPTYPE="PERIPHERAL" IS_ENABLE="1" MODCLASS="PERIPHERAL" MODTYPE="port_slicer" VLNV="pavel-demin:user:port_slicer:1.0">
      <DOCUMENTS/>
      <PARAMETERS>
        <PARAMETER NAME="DIN_WIDTH" VALUE="32"/>
        <PARAMETER NAME="DIN_FROM" VALUE="7"/>
        <PARAMETER NAME="DIN_TO" VALUE="0"/>
        <PARAMETER NAME="Component_Name" VALUE="system_slice_GPIO_out_2"/>
        <PARAMETER NAME="EDK_IPTYPE" VALUE="PERIPHERAL"/>
      </PARAMETERS>
      <PORTS>
        <PORT DIR="I" LEFT="31" NAME="din" RIGHT="0" SIGIS="undef" SIGNAME="fsk_detector_1_00_0_out_data">
          <CONNECTIONS>
            <CONNECTION INSTANCE="fsk_detector_1_00_0" PORT="out_data"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" LEFT="7" NAME="dout" RIGHT="0" SIGIS="undef" SIGNAME="slice_GPIO_out1_dout">
          <CONNECTIONS>
            <CONNECTION INSTANCE="io_bridge_out" PORT="out_data"/>
          </CONNECTIONS>
        </PORT>
      </PORTS>
      <BUSINTERFACES/>
    </MODULE>
    <MODULE COREREVISION="25" FULLNAME="/subset_0" HWVERSION="1.1" INSTANCE="subset_0" IPTYPE="BUS" IS_ENABLE="1" MODCLASS="BUS" MODTYPE="axis_subset_converter" VLNV="xilinx.com:ip:axis_subset_converter:1.1">
      <DOCUMENTS>
        <DOCUMENT SOURCE="https://www.xilinx.com/cgi-bin/docs/ipdoc?c=axis_subset_converter;v=v1_1;d=pg085-axi4stream-infrastructure.pdf"/>
      </DOCUMENTS>
      <PARAMETERS>
        <PARAMETER NAME="C_FAMILY" VALUE="zynq"/>
        <PARAMETER NAME="C_S_AXIS_TDATA_WIDTH" VALUE="96"/>
        <PARAMETER NAME="C_S_AXIS_TID_WIDTH" VALUE="1"/>
        <PARAMETER NAME="C_S_AXIS_TDEST_WIDTH" VALUE="1"/>
        <PARAMETER NAME="C_S_AXIS_TUSER_WIDTH" VALUE="1"/>
        <PARAMETER NAME="C_S_AXIS_SIGNAL_SET" VALUE="0b00000000000000000000000000000011"/>
        <PARAMETER NAME="C_M_AXIS_TDATA_WIDTH" VALUE="32"/>
        <PARAMETER NAME="C_M_AXIS_TID_WIDTH" VALUE="1"/>
        <PARAMETER NAME="C_M_AXIS_TDEST_WIDTH" VALUE="1"/>
        <PARAMETER NAME="C_M_AXIS_SIGNAL_SET" VALUE="0b00000000000000000000000000000011"/>
        <PARAMETER NAME="C_M_AXIS_TUSER_WIDTH" VALUE="1"/>
        <PARAMETER NAME="C_DEFAULT_TLAST" VALUE="0"/>
        <PARAMETER NAME="S_TDATA_NUM_BYTES" VALUE="12"/>
        <PARAMETER NAME="M_TDATA_NUM_BYTES" VALUE="4"/>
        <PARAMETER NAME="S_TID_WIDTH" VALUE="0"/>
        <PARAMETER NAME="M_TID_WIDTH" VALUE="0"/>
        <PARAMETER NAME="S_TDEST_WIDTH" VALUE="0"/>
        <PARAMETER NAME="M_TDEST_WIDTH" VALUE="0"/>
        <PARAMETER NAME="S_TUSER_WIDTH" VALUE="0"/>
        <PARAMETER NAME="M_TUSER_WIDTH" VALUE="0"/>
        <PARAMETER NAME="S_HAS_TREADY" VALUE="1"/>
        <PARAMETER NAME="S_HAS_TSTRB" VALUE="0"/>
        <PARAMETER NAME="S_HAS_TKEEP" VALUE="0"/>
        <PARAMETER NAME="S_HAS_TLAST" VALUE="0"/>
        <PARAMETER NAME="M_HAS_TREADY" VALUE="1"/>
        <PARAMETER NAME="M_HAS_TSTRB" VALUE="0"/>
        <PARAMETER NAME="M_HAS_TKEEP" VALUE="0"/>
        <PARAMETER NAME="M_HAS_TLAST" VALUE="0"/>
        <PARAMETER NAME="HAS_ACLKEN" VALUE="0"/>
        <PARAMETER NAME="DEFAULT_TLAST" VALUE="0"/>
        <PARAMETER NAME="TDATA_REMAP" VALUE="tdata[39:24],tdata[15:0]"/>
        <PARAMETER NAME="TUSER_REMAP" VALUE="1'b0"/>
        <PARAMETER NAME="TID_REMAP" VALUE="1'b0"/>
        <PARAMETER NAME="TDEST_REMAP" VALUE="1'b0"/>
        <PARAMETER NAME="TKEEP_REMAP" VALUE="1'b0"/>
        <PARAMETER NAME="TSTRB_REMAP" VALUE="1'b0"/>
        <PARAMETER NAME="TLAST_REMAP" VALUE="1'b0"/>
        <PARAMETER NAME="Component_Name" VALUE="system_subset_0_0"/>
        <PARAMETER NAME="EDK_IPTYPE" VALUE="BUS"/>
      </PARAMETERS>
      <PORTS>
        <PORT CLKFREQUENCY="122880000" DIR="I" NAME="aclk" SIGIS="clk" SIGNAME="pll_0_clk_out1">
          <CONNECTIONS>
            <CONNECTION INSTANCE="pll_0" PORT="clk_out1"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" NAME="aresetn" POLARITY="ACTIVE_LOW" SIGIS="rst" SIGNAME="slice_0_dout">
          <CONNECTIONS>
            <CONNECTION INSTANCE="slice_0" PORT="dout"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" NAME="s_axis_tvalid" SIGIS="undef" SIGNAME="fir_0_m_axis_data_tvalid">
          <CONNECTIONS>
            <CONNECTION INSTANCE="fir_0" PORT="m_axis_data_tvalid"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" NAME="s_axis_tready" SIGIS="undef" SIGNAME="fir_0_m_axis_data_tready">
          <CONNECTIONS>
            <CONNECTION INSTANCE="fir_0" PORT="m_axis_data_tready"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" LEFT="95" NAME="s_axis_tdata" RIGHT="0" SIGIS="undef" SIGNAME="fir_0_m_axis_data_tdata">
          <CONNECTIONS>
            <CONNECTION INSTANCE="fir_0" PORT="m_axis_data_tdata"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" NAME="m_axis_tvalid" SIGIS="undef" SIGNAME="subset_0_m_axis_tvalid">
          <CONNECTIONS>
            <CONNECTION INSTANCE="writer_0" PORT="s_axis_tvalid"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" NAME="m_axis_tready" SIGIS="undef" SIGNAME="subset_0_m_axis_tready">
          <CONNECTIONS>
            <CONNECTION INSTANCE="writer_0" PORT="s_axis_tready"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" LEFT="31" NAME="m_axis_tdata" RIGHT="0" SIGIS="undef" SIGNAME="subset_0_m_axis_tdata">
          <CONNECTIONS>
            <CONNECTION INSTANCE="writer_0" PORT="s_axis_tdata"/>
          </CONNECTIONS>
        </PORT>
      </PORTS>
      <BUSINTERFACES>
        <BUSINTERFACE BUSNAME="fir_0_M_AXIS_DATA" NAME="S_AXIS" TYPE="TARGET" VLNV="xilinx.com:interface:axis:1.0">
          <PARAMETER NAME="TDATA_NUM_BYTES" VALUE="12"/>
          <PARAMETER NAME="TDEST_WIDTH" VALUE="0"/>
          <PARAMETER NAME="TID_WIDTH" VALUE="0"/>
          <PARAMETER NAME="TUSER_WIDTH" VALUE="0"/>
          <PARAMETER NAME="HAS_TREADY" VALUE="1"/>
          <PARAMETER NAME="HAS_TSTRB" VALUE="0"/>
          <PARAMETER NAME="HAS_TKEEP" VALUE="0"/>
          <PARAMETER NAME="HAS_TLAST" VALUE="0"/>
          <PARAMETER NAME="FREQ_HZ" VALUE="122880000"/>
          <PARAMETER NAME="PHASE" VALUE="0.0"/>
          <PARAMETER NAME="CLK_DOMAIN" VALUE="system_pll_0_0_clk_out1"/>
          <PARAMETER NAME="LAYERED_METADATA" VALUE="xilinx.com:interface:datatypes:1.0 {TDATA {datatype {name {attribs {resolve_type immediate dependency {} format string minimum {} maximum {}} value {}} bitwidth {attribs {resolve_type automatic dependency {} format long minimum {} maximum {}} value 90} bitoffset {attribs {resolve_type immediate dependency {} format long minimum {} maximum {}} value 0} array_type {name {attribs {resolve_type immediate dependency {} format string minimum {} maximum {}} value chan} size {attribs {resolve_type generated dependency chan_size format long minimum {} maximum {}} value 1} stride {attribs {resolve_type generated dependency chan_stride format long minimum {} maximum {}} value 96} datatype {name {attribs {resolve_type immediate dependency {} format string minimum {} maximum {}} value {}} bitwidth {attribs {resolve_type automatic dependency {} format long minimum {} maximum {}} value 90} bitoffset {attribs {resolve_type immediate dependency {} format long minimum {} maximum {}} value 0} array_type {name {attribs {resolve_type immediate dependency {} format string minimum {} maximum {}} value path} size {attribs {resolve_type generated dependency path_size format long minimum {} maximum {}} value 4} stride {attribs {resolve_type generated dependency path_stride format long minimum {} maximum {}} value 24} datatype {name {attribs {resolve_type immediate dependency {} format string minimum {} maximum {}} value {}} bitwidth {attribs {resolve_type generated dependency out_width format long minimum {} maximum {}} value 18} bitoffset {attribs {resolve_type immediate dependency {} format long minimum {} maximum {}} value 0} real {fixed {fractwidth {attribs {resolve_type generated dependency out_fractwidth format long minimum {} maximum {}} value 0} signed {attribs {resolve_type generated dependency out_signed format bool minimum {} maximum {}} value true}}}}}}}}} TDATA_WIDTH 96 TUSER {datatype {name {attribs {resolve_type immediate dependency {} format string minimum {} maximum {}} value {}} bitwidth {attribs {resolve_type automatic dependency {} format long minimum {} maximum {}} value 0} bitoffset {attribs {resolve_type immediate dependency {} format long minimum {} maximum {}} value 0} struct {field_data_valid {name {attribs {resolve_type immediate dependency {} format string minimum {} maximum {}} value data_valid} enabled {attribs {resolve_type generated dependency data_valid_enabled format bool minimum {} maximum {}} value false} datatype {name {attribs {resolve_type immediate dependency {} format string minimum {} maximum {}} value {}} bitwidth {attribs {resolve_type generated dependency data_valid_bitwidth format long minimum {} maximum {}} value 0} bitoffset {attribs {resolve_type immediate dependency {} format long minimum {} maximum {}} value 0}}} field_chanid {name {attribs {resolve_type immediate dependency {} format string minimum {} maximum {}} value chanid} enabled {attribs {resolve_type generated dependency chanid_enabled format bool minimum {} maximum {}} value false} datatype {name {attribs {resolve_type immediate dependency {} format string minimum {} maximum {}} value {}} bitwidth {attribs {resolve_type generated dependency chanid_bitwidth format long minimum {} maximum {}} value 0} bitoffset {attribs {resolve_type generated dependency chanid_bitoffset format long minimum {} maximum {}} value 0} integer {signed {attribs {resolve_type immediate dependency {} format bool minimum {} maximum {}} value false}}}} field_user {name {attribs {resolve_type immediate dependency {} format string minimum {} maximum {}} value user} enabled {attribs {resolve_type generated dependency user_enabled format bool minimum {} maximum {}} value false} datatype {name {attribs {resolve_type immediate dependency {} format string minimum {} maximum {}} value {}} bitwidth {attribs {resolve_type generated dependency user_bitwidth format long minimum {} maximum {}} value 0} bitoffset {attribs {resolve_type generated dependency user_bitoffset format long minimum {} maximum {}} value 0}}}}}} TUSER_WIDTH 0}"/>
          <PARAMETER NAME="INSERT_VIP" VALUE="0"/>
          <PORTMAPS>
            <PORTMAP LOGICAL="TDATA" PHYSICAL="s_axis_tdata"/>
            <PORTMAP LOGICAL="TREADY" PHYSICAL="s_axis_tready"/>
            <PORTMAP LOGICAL="TVALID" PHYSICAL="s_axis_tvalid"/>
          </PORTMAPS>
        </BUSINTERFACE>
        <BUSINTERFACE BUSNAME="subset_0_M_AXIS" NAME="M_AXIS" TYPE="MASTER" VLNV="xilinx.com:interface:axis:1.0">
          <PARAMETER NAME="TDATA_NUM_BYTES" VALUE="4"/>
          <PARAMETER NAME="TDEST_WIDTH" VALUE="0"/>
          <PARAMETER NAME="TID_WIDTH" VALUE="0"/>
          <PARAMETER NAME="TUSER_WIDTH" VALUE="0"/>
          <PARAMETER NAME="HAS_TREADY" VALUE="1"/>
          <PARAMETER NAME="HAS_TSTRB" VALUE="0"/>
          <PARAMETER NAME="HAS_TKEEP" VALUE="0"/>
          <PARAMETER NAME="HAS_TLAST" VALUE="0"/>
          <PARAMETER NAME="FREQ_HZ" VALUE="122880000"/>
          <PARAMETER NAME="PHASE" VALUE="0.0"/>
          <PARAMETER NAME="CLK_DOMAIN" VALUE="system_pll_0_0_clk_out1"/>
          <PARAMETER NAME="LAYERED_METADATA" VALUE="undef"/>
          <PARAMETER NAME="INSERT_VIP" VALUE="0"/>
          <PORTMAPS>
            <PORTMAP LOGICAL="TDATA" PHYSICAL="m_axis_tdata"/>
            <PORTMAP LOGICAL="TREADY" PHYSICAL="m_axis_tready"/>
            <PORTMAP LOGICAL="TVALID" PHYSICAL="m_axis_tvalid"/>
          </PORTMAPS>
        </BUSINTERFACE>
      </BUSINTERFACES>
    </MODULE>
    <MODULE COREREVISION="1" FULLNAME="/writer_0" HWVERSION="1.0" INSTANCE="writer_0" IPTYPE="PERIPHERAL" IS_ENABLE="1" MODCLASS="PERIPHERAL" MODTYPE="axis_ram_writer" VLNV="pavel-demin:user:axis_ram_writer:1.0">
      <DOCUMENTS/>
      <PARAMETERS>
        <PARAMETER NAME="ADDR_WIDTH" VALUE="16"/>
        <PARAMETER NAME="AXI_ID_WIDTH" VALUE="3"/>
        <PARAMETER NAME="AXI_ADDR_WIDTH" VALUE="32"/>
        <PARAMETER NAME="AXI_DATA_WIDTH" VALUE="64"/>
        <PARAMETER NAME="AXIS_TDATA_WIDTH" VALUE="32"/>
        <PARAMETER NAME="FIFO_WRITE_DEPTH" VALUE="512"/>
        <PARAMETER NAME="Component_Name" VALUE="system_writer_0_0"/>
        <PARAMETER NAME="EDK_IPTYPE" VALUE="PERIPHERAL"/>
      </PARAMETERS>
      <PORTS>
        <PORT CLKFREQUENCY="122880000" DIR="I" NAME="aclk" SIGIS="clk" SIGNAME="pll_0_clk_out1">
          <CONNECTIONS>
            <CONNECTION INSTANCE="pll_0" PORT="clk_out1"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" NAME="aresetn" POLARITY="ACTIVE_LOW" SIGIS="rst" SIGNAME="slice_1_dout">
          <CONNECTIONS>
            <CONNECTION INSTANCE="slice_1" PORT="dout"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" LEFT="31" NAME="min_addr" RIGHT="0" SIGIS="undef" SIGNAME="slice_3_dout">
          <CONNECTIONS>
            <CONNECTION INSTANCE="slice_3" PORT="dout"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" LEFT="15" NAME="cfg_data" RIGHT="0" SIGIS="undef" SIGNAME="slice_9_dout">
          <CONNECTIONS>
            <CONNECTION INSTANCE="slice_9" PORT="dout"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" LEFT="15" NAME="sts_data" RIGHT="0" SIGIS="undef" SIGNAME="writer_0_sts_data">
          <CONNECTIONS>
            <CONNECTION INSTANCE="hub_0" PORT="sts_data"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" LEFT="2" NAME="m_axi_awid" RIGHT="0" SIGIS="undef" SIGNAME="ps_0_S_AXI_ACP_AWID">
          <CONNECTIONS>
            <CONNECTION INSTANCE="ps_0" PORT="S_AXI_ACP_AWID"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" LEFT="3" NAME="m_axi_awlen" RIGHT="0" SIGIS="undef" SIGNAME="ps_0_S_AXI_ACP_AWLEN">
          <CONNECTIONS>
            <CONNECTION INSTANCE="ps_0" PORT="S_AXI_ACP_AWLEN"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" LEFT="2" NAME="m_axi_awsize" RIGHT="0" SIGIS="undef" SIGNAME="ps_0_S_AXI_ACP_AWSIZE">
          <CONNECTIONS>
            <CONNECTION INSTANCE="ps_0" PORT="S_AXI_ACP_AWSIZE"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" LEFT="1" NAME="m_axi_awburst" RIGHT="0" SIGIS="undef" SIGNAME="ps_0_S_AXI_ACP_AWBURST">
          <CONNECTIONS>
            <CONNECTION INSTANCE="ps_0" PORT="S_AXI_ACP_AWBURST"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" LEFT="3" NAME="m_axi_awcache" RIGHT="0" SIGIS="undef" SIGNAME="ps_0_S_AXI_ACP_AWCACHE">
          <CONNECTIONS>
            <CONNECTION INSTANCE="ps_0" PORT="S_AXI_ACP_AWCACHE"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" LEFT="31" NAME="m_axi_awaddr" RIGHT="0" SIGIS="undef" SIGNAME="ps_0_S_AXI_ACP_AWADDR">
          <CONNECTIONS>
            <CONNECTION INSTANCE="ps_0" PORT="S_AXI_ACP_AWADDR"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" NAME="m_axi_awvalid" SIGIS="undef" SIGNAME="ps_0_S_AXI_ACP_AWVALID">
          <CONNECTIONS>
            <CONNECTION INSTANCE="ps_0" PORT="S_AXI_ACP_AWVALID"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" NAME="m_axi_awready" SIGIS="undef" SIGNAME="ps_0_S_AXI_ACP_AWREADY">
          <CONNECTIONS>
            <CONNECTION INSTANCE="ps_0" PORT="S_AXI_ACP_AWREADY"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" LEFT="2" NAME="m_axi_wid" RIGHT="0" SIGIS="undef" SIGNAME="ps_0_S_AXI_ACP_WID">
          <CONNECTIONS>
            <CONNECTION INSTANCE="ps_0" PORT="S_AXI_ACP_WID"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" LEFT="7" NAME="m_axi_wstrb" RIGHT="0" SIGIS="undef" SIGNAME="ps_0_S_AXI_ACP_WSTRB">
          <CONNECTIONS>
            <CONNECTION INSTANCE="ps_0" PORT="S_AXI_ACP_WSTRB"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" NAME="m_axi_wlast" SIGIS="undef" SIGNAME="ps_0_S_AXI_ACP_WLAST">
          <CONNECTIONS>
            <CONNECTION INSTANCE="ps_0" PORT="S_AXI_ACP_WLAST"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" LEFT="63" NAME="m_axi_wdata" RIGHT="0" SIGIS="undef" SIGNAME="ps_0_S_AXI_ACP_WDATA">
          <CONNECTIONS>
            <CONNECTION INSTANCE="ps_0" PORT="S_AXI_ACP_WDATA"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" NAME="m_axi_wvalid" SIGIS="undef" SIGNAME="ps_0_S_AXI_ACP_WVALID">
          <CONNECTIONS>
            <CONNECTION INSTANCE="ps_0" PORT="S_AXI_ACP_WVALID"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" NAME="m_axi_wready" SIGIS="undef" SIGNAME="ps_0_S_AXI_ACP_WREADY">
          <CONNECTIONS>
            <CONNECTION INSTANCE="ps_0" PORT="S_AXI_ACP_WREADY"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" NAME="m_axi_bvalid" SIGIS="undef" SIGNAME="ps_0_S_AXI_ACP_BVALID">
          <CONNECTIONS>
            <CONNECTION INSTANCE="ps_0" PORT="S_AXI_ACP_BVALID"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" NAME="m_axi_bready" SIGIS="undef" SIGNAME="ps_0_S_AXI_ACP_BREADY">
          <CONNECTIONS>
            <CONNECTION INSTANCE="ps_0" PORT="S_AXI_ACP_BREADY"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" LEFT="31" NAME="s_axis_tdata" RIGHT="0" SIGIS="undef" SIGNAME="subset_0_m_axis_tdata">
          <CONNECTIONS>
            <CONNECTION INSTANCE="subset_0" PORT="m_axis_tdata"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" NAME="s_axis_tvalid" SIGIS="undef" SIGNAME="subset_0_m_axis_tvalid">
          <CONNECTIONS>
            <CONNECTION INSTANCE="subset_0" PORT="m_axis_tvalid"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" NAME="s_axis_tready" SIGIS="undef" SIGNAME="subset_0_m_axis_tready">
          <CONNECTIONS>
            <CONNECTION INSTANCE="subset_0" PORT="m_axis_tready"/>
          </CONNECTIONS>
        </PORT>
      </PORTS>
      <BUSINTERFACES>
        <BUSINTERFACE BUSNAME="subset_0_M_AXIS" NAME="s_axis" TYPE="SLAVE" VLNV="xilinx.com:interface:axis:1.0">
          <PARAMETER NAME="TDATA_NUM_BYTES" VALUE="4"/>
          <PARAMETER NAME="TDEST_WIDTH" VALUE="0"/>
          <PARAMETER NAME="TID_WIDTH" VALUE="0"/>
          <PARAMETER NAME="TUSER_WIDTH" VALUE="0"/>
          <PARAMETER NAME="HAS_TREADY" VALUE="1"/>
          <PARAMETER NAME="HAS_TSTRB" VALUE="0"/>
          <PARAMETER NAME="HAS_TKEEP" VALUE="0"/>
          <PARAMETER NAME="HAS_TLAST" VALUE="0"/>
          <PARAMETER NAME="FREQ_HZ" VALUE="122880000"/>
          <PARAMETER NAME="PHASE" VALUE="0.0"/>
          <PARAMETER NAME="CLK_DOMAIN" VALUE="system_pll_0_0_clk_out1"/>
          <PARAMETER NAME="LAYERED_METADATA" VALUE="undef"/>
          <PARAMETER NAME="INSERT_VIP" VALUE="0"/>
          <PORTMAPS>
            <PORTMAP LOGICAL="TDATA" PHYSICAL="s_axis_tdata"/>
            <PORTMAP LOGICAL="TVALID" PHYSICAL="s_axis_tvalid"/>
            <PORTMAP LOGICAL="TREADY" PHYSICAL="s_axis_tready"/>
          </PORTMAPS>
        </BUSINTERFACE>
        <BUSINTERFACE BUSNAME="writer_0_m_axi" DATAWIDTH="64" NAME="m_axi" TYPE="MASTER" VLNV="xilinx.com:interface:aximm:1.0">
          <PARAMETER NAME="DATA_WIDTH" VALUE="64"/>
          <PARAMETER NAME="PROTOCOL" VALUE="AXI3"/>
          <PARAMETER NAME="FREQ_HZ" VALUE="122880000"/>
          <PARAMETER NAME="ID_WIDTH" VALUE="3"/>
          <PARAMETER NAME="ADDR_WIDTH" VALUE="32"/>
          <PARAMETER NAME="AWUSER_WIDTH" VALUE="0"/>
          <PARAMETER NAME="ARUSER_WIDTH" VALUE="0"/>
          <PARAMETER NAME="WUSER_WIDTH" VALUE="0"/>
          <PARAMETER NAME="RUSER_WIDTH" VALUE="0"/>
          <PARAMETER NAME="BUSER_WIDTH" VALUE="0"/>
          <PARAMETER NAME="READ_WRITE_MODE" VALUE="WRITE_ONLY"/>
          <PARAMETER NAME="HAS_BURST" VALUE="1"/>
          <PARAMETER NAME="HAS_LOCK" VALUE="0"/>
          <PARAMETER NAME="HAS_PROT" VALUE="0"/>
          <PARAMETER NAME="HAS_CACHE" VALUE="1"/>
          <PARAMETER NAME="HAS_QOS" VALUE="0"/>
          <PARAMETER NAME="HAS_REGION" VALUE="0"/>
          <PARAMETER NAME="HAS_WSTRB" VALUE="1"/>
          <PARAMETER NAME="HAS_BRESP" VALUE="0"/>
          <PARAMETER NAME="HAS_RRESP" VALUE="0"/>
          <PARAMETER NAME="SUPPORTS_NARROW_BURST" VALUE="1"/>
          <PARAMETER NAME="NUM_READ_OUTSTANDING" VALUE="2"/>
          <PARAMETER NAME="NUM_WRITE_OUTSTANDING" VALUE="2"/>
          <PARAMETER NAME="MAX_BURST_LENGTH" VALUE="16"/>
          <PARAMETER NAME="PHASE" VALUE="0.0"/>
          <PARAMETER NAME="CLK_DOMAIN" VALUE="system_pll_0_0_clk_out1"/>
          <PARAMETER NAME="NUM_READ_THREADS" VALUE="1"/>
          <PARAMETER NAME="NUM_WRITE_THREADS" VALUE="1"/>
          <PARAMETER NAME="RUSER_BITS_PER_BYTE" VALUE="0"/>
          <PARAMETER NAME="WUSER_BITS_PER_BYTE" VALUE="0"/>
          <PARAMETER NAME="INSERT_VIP" VALUE="0"/>
          <PORTMAPS>
            <PORTMAP LOGICAL="AWID" PHYSICAL="m_axi_awid"/>
            <PORTMAP LOGICAL="AWADDR" PHYSICAL="m_axi_awaddr"/>
            <PORTMAP LOGICAL="AWLEN" PHYSICAL="m_axi_awlen"/>
            <PORTMAP LOGICAL="AWSIZE" PHYSICAL="m_axi_awsize"/>
            <PORTMAP LOGICAL="AWBURST" PHYSICAL="m_axi_awburst"/>
            <PORTMAP LOGICAL="AWCACHE" PHYSICAL="m_axi_awcache"/>
            <PORTMAP LOGICAL="AWVALID" PHYSICAL="m_axi_awvalid"/>
            <PORTMAP LOGICAL="AWREADY" PHYSICAL="m_axi_awready"/>
            <PORTMAP LOGICAL="WID" PHYSICAL="m_axi_wid"/>
            <PORTMAP LOGICAL="WDATA" PHYSICAL="m_axi_wdata"/>
            <PORTMAP LOGICAL="WSTRB" PHYSICAL="m_axi_wstrb"/>
            <PORTMAP LOGICAL="WLAST" PHYSICAL="m_axi_wlast"/>
            <PORTMAP LOGICAL="WVALID" PHYSICAL="m_axi_wvalid"/>
            <PORTMAP LOGICAL="WREADY" PHYSICAL="m_axi_wready"/>
            <PORTMAP LOGICAL="BVALID" PHYSICAL="m_axi_bvalid"/>
            <PORTMAP LOGICAL="BREADY" PHYSICAL="m_axi_bready"/>
          </PORTMAPS>
        </BUSINTERFACE>
      </BUSINTERFACES>
      <MEMORYMAP/>
      <PERIPHERALS>
        <PERIPHERAL INSTANCE="ps_0"/>
      </PERIPHERALS>
    </MODULE>
  </MODULES>

</EDKSYSTEM>
